View SMC91C95_205111.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SMC91C95
PRELIMINARY
ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM
FEATURES
* * * * * * * * ISA/PCMCIA Single Chip Ethernet Controller With Modem Support 6 Kbytes Built-In RAM Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards Full Duplex Support Hardware Memory Management Unit Built-In AUI and 10BASE-T Network Interfaces Simultasking - Early Transmit and Early Receive Functions Advanced Power Management Features/Including Magic Packet Frame Control Software Compatible with SMC91C92/ SMC91C94 (in ISA Mode) Configuration Registers Implement Cardbus Multi-Function Specification V3.0 with Backward Compatibility to V2.1 Interfaces Directly to Lucent Technologies and Rockwell International Modem Chipsets On-Chip Attribute Memory (CIS) of up to 512 Bytes (On Even Addresses) For Card Configuration Information; Expandable Externally Option for Serial or Parallel EEPROM for CIS * * * * * Optional External Flash Capability for XIP (Execute in Place) Automatic Technology to Detect TX/RX 10BASE-T Tranceiver Pair Miswiring Low Power CMOS Design Supports Magic Packet Wakeup 128 Pin VTQFP Package
Bus Interface * * * * * * * * * * * * Direct Interface to ISA and PCMCIA with No Wait States High Impedance Speaker Interface Flexible Bus Interface 16-Bit Data and Control Paths Fast Access Time (40 ns) Pipelined Data Path Handles Block Word Transfers for Any Alignment High Performance Chained ("Back-toBack") Transmit and Receive Flat Memory Structure for Low CPU Overhead Dynamic Memory Allocation Between Transmit and Receive Buffered Architecture, Insensitive to Bus Latencies (No Overruns/Underruns) Supports Boot PROM for Diskless ISA Applications
* *
* *
*
Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation
TABLE OF CONTENTS
FEATURES.......................................................................................................................................................1 PIN CONFIGURATION ....................................................................................................................................3 GENERAL DESCRIPTION...............................................................................................................................4 OVERVIEW ......................................................................................................................................................4 PIN REQUIREMENTS......................................................................................................................................7 DESCRIPTION OF PIN FUNCTIONS..............................................................................................................9
BUFFER TYPES........................................................................................................................................... 17
FUNCTIONAL DESCRIPTION.......................................................................................................................21 INTERRUPT STRUCTURE ............................................................................................................................32
RESET LOGIC.............................................................................................................................................. 33 POWERDOWN LOGIC................................................................................................................................ 34 PCMCIA A TTRIBUTE MEMORY: ADDRESS 0- 7FFEH............................................................................................ 35 PCMCIA C ONFIGURATION REGISTERS: ADDRESS 8000-803EH............................................................................. 35 INTERNAL VS EXTERNAL ATTRIBUTE MEMORY MAP.................................................................................................. 36
THEORY OF OPERATION ............................................................................................................................69
"MAGIC PACKET" SUPPORT.................................................................................................................................. 70 INTERNAL VS. EXTERNAL ATTRIBUTE MEMORY MAP ........................................................................ 80 PCMCIA CONFIGURATION REGISTERS DESCRIPTION ....................................................................... 82 FUNCTIONAL DESCRIPTION OF THE BLOCKS ...................................................................................... 91 BOARD SETUP INFORMATION ............................................................................................................... 100
OPERATIONAL DESCRIPTION..................................................................................................................104 TIMING DIAGRAMS ....................................................................................................................................108
Related Documentation
1. 2. 3. 4. PCMCIA 2.1 Standard (for PCMCIA timing and functionality) PCMCIA 3.X spec (for multi-function extensions) AT&T HSM288xCF Modem Chip Set Data Sheet - July 5, 1994 Rockwell RC224ATF and C39 Modem Chip Sets Designer's Guide
2
Network Interface * Integrates 10BASE-T Transceiver Functions: Driver and Receiver Link Integrity Test Receive Polarity Detection and Correction Integrates AUI Interface Implements 10 Mbps Manchester Encoding/Decoding and Clock Recovery Automatic Retransmission, Bad Packet Rejection, and Transmit Padding External and Internal Loopback Modes
*
Four Direct Driven LEDs for Status/ Diagnostics
Software Drivers * * * Uses Certified SMC9000 Drivers Which Operate with Every Major Network Operating System Software Driver Compatible with SMC91C92, SMC91C94 and SMC91C100 (100 Mbps) Controllers in ISA Mode Software Driver Utilizes Full Capability of 32 Bit Microprocessor
* * * *
PIN CONFIGURATION
NC AVSS COLN COLP RECN RECP TPERXN TPERXP AVDD AVSS RBIAS AVDD nXENDEC nEN16 PWRDWN/TXCLK nROM/nPCMCIA VSS ENEEP EESK EECS EEDO/SDOUT EEDI IOS2 IOS1 VDD IOS0 XTAL2 XTAL1 WAKEUP nWAKEUP_EN RESET NC AVDD TXP/nCOLL TXN/nCRS TPETXP TEPTXDP TPETXN TPETXDN AVSS nTXLED/nTXEN nRXLED/RXCLK nLINKLED/TXD nBSELED/RXD VDD SPKRIN SPKROUT nMIS16 MRDY MINT VSS MRINGIN nMRINGOA MRINGOB nMCS nMRESET VDD MIDLEN1 nMPWDN nMPDOUT MFBK1 VSS NC ND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
SMC91C95 128 Pin VTQFP
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC NC VSS INTR3 INTR2/nSTSCHG INTR1/nINPACK INTR0/nIREQ VDD nIORD nIOWR nMEMR/nOE nIOSC16/nIOIS16 VSS IOCHRDY/nWAIT BALE/nWE nSBHE/nCE2 VDD D15 D14 D13 D12 VSS D11 D10 D9 VDD D8 D7 D6 VSS D5 D4
NC AEN/nREG A0 A1 VDD A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 VDD A14 A15 A16/nFWE A17/nFCS A18 A19/nCE1 VSS D0 D1 D2 VDD D3 NC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
3
GENERAL DESCRIPTION
The SMC91C95 is a VLSI Ethernet Controller that combines ISA and PCMCIA interfaces, as well as an interface to a companion modem chip set, in one chip. The SMC91C95 integrates all the MAC and physical layer functions as well as the packet RAM needed to implement a high performance 10BASE-T (twisted pair) node. For 10BASE5 (thick coax), 10BASE2 (thin coax), and 10BASE-F (fiber) implementations, the SMC91C95 interfaces to external transceivers via its AUI port. Only one additional IC is required on most applications. The SMC91C95 occupies 16 I/O locations and no memory space except for PCMCIA attribute memory space. The same I/O space is used for both ISA and PCMCIA operations. The SMC91C95 can directly interface the ISA and PCMCIA buses and deliver no wait state operation. Its shared memory is sequentially accessed with 40ns access times to any of its registers, including its packet memory. No DMA services are used by the SMC91C95; virtually decoupling network traffic from local or system bus utilization. For packet memory management, the SMC91C95 integrates a unique hardware Memory Management Unit (MMU) with enhanced performance and decreased software overhead when compared to ring buffer and linked list architectures. The SMC91C95 is portable to different CPU and bus platforms due to its flexible bus interface, flat memory structure (no pointers), and its loosely coupled buffered architecture (not sensitive to latency). The SMC91C95 interfaces directly with Rockwell International L39/C39 controller-based modems and Lucent Technologies' HSM288xCF modem.
OVERVIEW
A unique architecture allows the SMC91C95 to combine high performance, flexibility, high integration and simple software interface. The SMC91C95 incorporates the SMC91C92/4 functionality for ISA environments with several new features, as well as a PCMCIA interface and attribute registers that comply with the PCMCIA Multi-Function specification. Mode selection between ISA and PCMCIA is static and is done only once at the end of power on reset. The SMC91C95 consists of the same logical I/O register structure in ISA and PCMCIA modes. However, some of the signals used to access the PCMCIA differ from the ISA mode. Additional registers exist in the PCMCIA attribute space. The ROM memory space only exists in ISA mode and the attribute space only exists in PCMCIA mode. I/O decoders are included in the SMC91C95's PCMCIA interface, with independent decoders for the LAN and for the modem functions. These decoders are used whenever the SMC91C95 is used as a multi-function card, and they can be bypassed when only one function is enabled. The SMC91C95 also merges the LAN's internal interrupt source with the external modem interrupt connected to the SMC91C95. The MMU (Memory Management Unit) architecture used by the SMC91C95 combines the simplicity and low overhead of fixed areas with the flexibility of linked lists providing improved performance over other methods. The SMC91C95 is designed to support full duplex switched Ethernet where transmit and
4
receive are fully independent. It has 6 kbytes of internal memory and the MMU manages memory in 256 byte pages. The memory size accommodates the increase in interrupt latency resulting from simultaneous LAN and modem operation as well as the potential for simultaneous transmit and receive traffice in some full duplex applications. Packet reception and transmission are determined by memory availability. All other resources are always available if memory is available. To complement this flexible architecture, all ISA bus interface functions are incorporated in the SMC91C95, as well as a 4608 byte packet RAM and serial EEPROMbased setup. The user can select or modify configuration choices. The SMC91C95 stores the Configuration Information Structure (CIS) on reset or powerup from the serial EEPROM. This allows the host to access data to allow the setup of the PCMCIA multi-function card. In ISA mode, the serial EEPROM acts as storage for configuration and IEEE Ethernet address information compatible with the existing SMC9000 family of ISA Ethernet controllers. In PCMCIA mode, the serial EEPROM stores the CIS, as well as the IEEE address, information, but it does not store any I/O or IRQ information since this information is handled by the host's socket controller. For CIS requirements above 512 bytes, an optional external parallel EEPROM can be used in conjunction with the internal CIS. This allows additional external, non-volatile storage for applications that require XIP and use the modem function. If the serial EEPROM is not used in PCMCIA mode, the parallel EEPROM must be used. In this case, the parallel EEPROM is selected for the first 512 bytes of storage as well, allowing the CIS to be stored in the parallel EEPROM and, on power-up, to be
read directly by the host. parallel EEPROM can be applications, if needed.
The remaining used for XIP
The SMC91C95 integrates most of the 802.3 functionality, incorporating the MAC layer protocol, the physical layer encoding and decoding functions with the ability to handle the AUI interface. For twisted pair networks, the SMC91C95 integrates the twisted pair transceiver as well as the link integrity test functions. The SMC91C95 is a true 10BASE-T single chip able to interface a system or a local bus. Directly-driven LEDs for installation and runtime diagnostics are provided, as well as 802.3 statistics gathering to facilitate network management. The SMC91C95 offers: High integration: Single chip adapter including: Packet RAM ISA bus interface PCMCIA interface EEPROM interface Encoder decoder with AUI interface Full duplex, magic packet 10BASE-T transceiver Lucent Technologies and Rockwell International modem interface High performance: Chained ("back-to-back") packet handling with no CPU intervention: Queues transmit packets Queues receive packets Full duplex operation for higher network throughput Stores results in memory along with packet Queues Ethernet and modem interrupts Optional single interrupt upon completion of transmit chain
5
Fast block move operation for load/unload: CPU sees packet bytes as if stored contiguously Handles 16 bit transfers regardless of address alignment Access to packet through fixed window Fast bus interface: Compatible with ISA type and faster buses Flexibility: Flexible packet and header processing: Can be set to Simultasking - Early Receive and transmit modes Can access any byte in the packet Can immediately remove undesired packets from queue Can move packets from receive to transmit queue Can alter receive processing order without copying data Can discard or enqueue again a failed transmission
Resource allocation: Memory dynamically allocated for transmit and receive Can automatically release memory on successful transmission Configuration: ISA: Uses non-volatile jumperless setup via serial EEPROM PCMCIA: Uses serial EEPROM for attribute memory storage. PCMCIA I/O ignores address lines A4-A15 and relies on the PCMCIA host, decoding for the slot nROM/nPCMCIA on the SMC91C95 is left open with a pullup for ISA mode. This pin is sampled at the end of Power On Reset. If found low, the SMC91C95 is configured for PCMCIA mode.
6
PIN REQUIREMENTS
FUNCTION SYSTEM ADDRESS BUS ISA A0-A15 A16 A17 A18 A19 AEN D0-D15 RESET BALE nIORD nIOWR nMEMR IOCHRDY nIOCS16 nSBHE INTR0 INTR1 INTR2 INTR3 nMRESET MINT nMCS MRDY nMPWDN MIDLEN1 MRINGIN nMRINGOA MRINGOB SPKRIN SPKROUT nMPDOUT MFBK1 nMIS16 EEDI EEDO EECS EESK ENEEP IOS0 IOS1 IOS2 7 PCMCIA A0-A15 nFWE nFCS nCE1 nREG D0-D15 RESET nWE nIORD nIOWR nOE nWAIT nIOIS16 nCE2 nIREQ nINPACK nSTSCHG nMRESET MINT nMCS MRDY nMPWDN MIDLEN1 MRINGIN nMRINGOA MRINGOB SPKRIN SPKROUT nMPDOUT MFBK1 nMIS16 EEDI EEDO EECS EESK ENEEP IOS0 IOS1 IOS2 16 12 NUMBER OF PINS 21
SYSTEM DATA BUS SYSTEM CONTROL BUS
MODEM INTERFACE
14
SERIAL EEPROM
8
FUNCTION CRYSTAL OSC. POWER GROUND 10BASE-T INTERFACE
ISA XTAL1 XTAL2 VDD AVDD GND AGND TPERXP TPERXN TPETXP TPETXN TPETXDP TPETXDN RECP RECN COLP COLN TXP/nCOLL TXN/nCRS nLNKLED/TXD nRXLED/RXCLK nBSELED/RXD nTXLED/nTXEN RBIAS WAKEUP nWAKEUPEN PWRDWN/TXCLK nXENDEC nEN16 ROM/nPCMCIA
PCMCIA XTAL1 XTAL2 VDD AVDD GND AGND TPERXP TPERXN TPETXP TPETXN TPETXDP TPETXDN RECP RECN COLP COLN TXP/nCOLL TXN/nCRS nLNKLED/TXD nRXLED/RXCLK nBSELED/RXD nTXLED/nTXEN RBIAS WAKEUP nWAKEUPEN PWRDWN/TXCLK nXENDEC nEN16 ROM/nPCMCIA
NUMBER OF PINS 2 12 12 6
AUI INTERFACE
6
LEDs
4
MISC.
7
TOTAL PINS
120
8
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 113 NAME SYMBOL nROM/ nPCMCIA TYPE I/O4 with pullup DESCRIPTION This pin is sampled at the end of RESET. When this pin is sampled low the SMC91C95 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode. For ISA operation this pin is left open and is used as a ROM chip select output that goes active when nMEMR is low and the address bus contains a valid ROM address. Input address lines 0 through 15.
35, 36, 38-43, 45-50, 52, 53 54
Address 015
A0-A15
I
Address 16 nFlash Memory Write
A16 nFWE
I O4
ISA - Input address line 16. PCMCIA - Output. Flash Memory Write Enable used for programming the attribute memory. Goes active (low) when nWE=0 and WRATTRIB=1 (in ECOR bit 3). ISA - Input address line 17. PCMCIA - Output. Flash Memory Chip Select used to access attribute memory. Goes active (low) when nREG=0, nCE1=0 and A15=0. Input address line 18. ISA - Input address line 19. PCMCIA - Card Enable 1 input. Used to select card on even byte accesses.
55
Address 17 nFlash Memory Chip Select
A17 nFCS
I O4
56 57
Address 18 Address 19 Card Enable 1
A18 A19 nCE1
I I with pullup
34
Address Enable
AEN
I with pullup
ISA - Address enable input. Used as an address qualifier. Address decoding is only enabled when AEN is low. PCMCIA - Attribute memory and IO select input. Asserted when the card attribute space or IO space is being accessed.
nREG
9
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 81 NAME nByte High Enable nCard Enable 2 83 Ready nWait SYMBOL nSBHE TYPE I with pullup DESCRIPTION ISA - Byte High Enable input. Asserted (low) by the system to indicate a data transfer on the upper data byte. PCMCIA - Card Enable 2 input. Used to select card on odd byte accesses. OD24 with pullup ISA - Output. Optionally used by the SMC91C95 to extend host cycles. PCMCIA - Output. Optionally used by the SMC91C95 to extend host cycles. I/O24 Bidirectional. 16 bit data bus used to access the SMC91C95 internal registers. The data bus has weak internal pullups. Supports direct connection to the system bus without external buffering.
nCE2
IOCHRDY nWAIT
59, 60, 61, 63, 65, 66, 68-70, 72-74, 76-79 98
Data Bus
D0-D15
Reset
RESET
IS with pullup
Input. Active high Reset. This input is not considered active unless it is active for at least 100ns to filter narrow glitches. A POR circuit generates an internal reset upon power up for at least 15msec. All hardware reset references in this spec relate to the OR function of the POR and the RESET pin. ISA - Input. Address strobe. For systems that require address latching, the falling edge of BALE latches address lines and nSBHE. PCMCIA - Write Enable input. Used for writing into COR and CSR registers as well as attribute memory space.
82
Address Latch nWrite Enable
BALE
IS with pullup
nWE
90
Interrupt
INTR0
O24
ISA - Active high interrupt signal. The interrupt line selection is determined by the value of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not selected.
10
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME nInterrupt Request SYMBOL nIREQ TYPE DESCRIPTION PCMCIA - Active low interrupt request output. Pin acts as a Ready pin during power-up. The pin should be pulled low within 10us of the application of the VCC or Reset (which ever occurs later). It remains low(0) until the CIS is loaded in the Internal SRAM. The high(1) state indicates to the host controller that the device is ready. O24 ISA - Output. Active high interrupt signal. The interrupt line selection is determined by the value of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not selected. PCMCIA - Output asserted to acknowledge read cycles for an enabled function. O24 ISA - Output. Active high interrupt signal. The interrupt line selection is determined by the value of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not selected. PCMCIA - Status changed bit. Depending on the setting of the RingEn bit (Modem CCSR), this pin either reflects the ringing status (ExCA mode) or the state of the Modem Changed bit. The ringing status is obtained by stretching the MRINGIN to convert a 20Hz toggle rate to a constant level. O24 ISA - Output. Active high interrupt signal. The interrupt line selection is determined by the value of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not selected. ISA - Active low output asserted in 16 bit mode when AEN is low and A4-A15 decode to the SMC91C95 address programmed into the high byte of the Base Address Register.
91
Interrupt 1
INTR1
nINPACK
92
Interrupt 2
INTR2
nStatus Changed
nSTSCHG
93
Interrupt 3
INTR3
85
nI/O 16
nIOCS16
OD24
11
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL nIOIS16 TYPE DESCRIPTION PCMCIA - Active low output asserted whenever the SMC91C95 is in 16 bit mode, and "Enable Function" bit in the ECOR register is high, nREG is low and A4-A15 decode to the LAN address specified in I/O Base Registers 0 and 1 in PCMCIA attribute space. IS with pullup IS with pullup IS with pullup Input. Active low read strobe used to access the SMC91C95 IO space. Input. Active low write strobe used to access the SMC91C95 IO space. ISA - Active low signal used by the host processor to read from the external ROM. PCMCIA - Output Enable input used to read from the COR, CSR and attribute memory. O4 Reset output to Modem. Asserted whenever RESET pin is high, internal POR is active, or SRESET bit is high (MCOR bit 7). Interrupt input from Modem. Reflected in INTR (CSR bit 1) and asserts the appropriate interrupt pin if enabled. Chip select output to modem.
88
nI/O Read
nIORD
87
nI/O Write
nIOWR
86
nMemory Read nOutput Enable
nMEMR
nOE
24
nModem Reset
nMRESET
18
Modem Interrupt
MINT
I with pull down
23
nModem Chip Select Modem Ready
nMCS
O4
17
MRDY
I with pullup
Modem ready input. Low indicates the modem is not ready, either after reset or exiting from stop or sleep modes. Powerdown output to modem controller. This pin is active (low) when either the PWRDWN bit (CSR bit 2) is set or the modem is disabled (not configured).
27
nModem Powerdown
nMPWDN
O4
12
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 26 NAME SYMBOL MIDLEN1 TYPE O4 DESCRIPTION Powerdown output to modem controller. This pin is active (high) when either the PWRDWN bit (CSR bit 2) is set or the modem is disabled (not configured). Ring input from the modem controller. Toggles when ringing, low when not ringing. Ring output signal. When there is no ringing on the MRINGIN pin and the modem is not in Powerdown mode this output is high. During ringing this signal is the inverse of the MRINGIN input. When the PWRDWN bit is set or the function is disabled, this output is low. This signal is activated about 12 msec after removing Powerdown. Ring output signal. When the modem is not in Powerdown mode (PWRDWN bit is zero and the function is enabled) this output follows the value of the MRINGIN input. When entering Powerdown mode, a rising edge is generated on the pin. A rising edge is also generated when exiting Powerdown mode also. Refer to Figure 2. Speaker Input. This is a digitized (single level) audio input from the modem controller. Speaker Output. This pin reflects the SPKRIN pin when enabled by the AUDIO bit (Modem CSR bit 3). When disabled this pin is tristated. Used to control Powerdown mode. Tie to a 180K pull-up and a 0.1uF cap to ground. Tie high when not used. This signal is used in the RC time constant. Tie to nMPDOUT through a 5.1M resistor. This signal is used in the RC time constant in conjuction with the nMPDOUT pin.
20
Modem Ring Input nModem Ring Output A
MRINGIN
I
21
nMRINGOA
O4
22
Modem Ring Output B
MRINGOB
O4
14
Speaker Input Speaker Output
SPKRIN
I with pullup
15
SPKROUT
O4 tri-stable with pullup
28
nMPDOUT
I Schmitt
29
MFBK1
O4 with pullup
13
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 16 NAME n16 Bit Modem SYMBOL nMIS16 TYPE I with pullup DESCRIPTION Input. When low, it indicates a 16 bit modem, otherwise the modem is 8 bit wide. Used to determine if nIOIS16 (PCMCIA) and nIOCS16 (ISA) need to be asserted for modem cycles. The value of this pin may change from cycle to cycle. Output. 4s clock used to shift data in and out of the serial EEPROM. Output. Serial EEPROM chip select.
110
EEPROM Clock EEPROM Chip Select EEPROM Data Out EEPROM Data In I/O Base
EESK
O4
109
EECS
O4
108
EEDO/ SDOUT EEDI
O4
Output. Connected to the DI input of the serial EEPROM. Input. Connected to the DO output of the serial EEPROM. Input. External switches can be connected to these lines to select between predefined EEPROM configurations. The values of these pins are readable. These pins are used in ISA mode only. If in PCMCIA mode, these pins are not used. Internal ENDEC - Transmit LED output. External ENDEC - Active low Transmit Enable output. Internal ENDEC - Board Select LED activated by accesses to I/O space (nIORD or nIOWR active with AEN low and valid address decode for ISA, and with nREG low and and "Enable Function" bit in the ECOR register is high for PCMCIA). The pulse is stretched beyond the access duration to make the LED visible. External ENDEC - NRZ receive data input.
107
I with pulldown I with pullup
103, 105, 106
IOS0-IOS2
9
nTransmit LED nTransmit Enable
nTXLED nTXEN
OD16 O162
12
nRoard Select LED
nBSELED
OD16
Receive Data
RXD
I with pullup
14
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 10 NAME nReceive LED Receive Clock 11 nLink LED Transmit Data 111 Enable EEPROM SYMBOL nRXLED RXCLK TYPE OD16 I with pullup DESCRIPTION Internal ENDEC - Receive LED output. External ENDEC - Receive clock input.
nLNKLED TXD
OD16 0162
Internal ENDEC - Link LED output. External ENDEC - Transmit Data output.
ENEEP
I with pullup
Input. This active high input enables the EEPROM to be read or written by the SMC91C95. Internally pulled up. Must be connected to ground if no serial EEPROM is used. In PCMCIA mode, a parallel EEPROM is required if no serial EEPROM is used. Input. When low the SMC91C95 is configured for 16 bit bus operation. If left open the SMC91C95 works in 8 bit bus mode. 16 bit configuration can also be programmed via serial EEPROM (In ISA Mode only) or via software initialization of the CONFIGURATION REGISTER. An external parallel resonance 20 MHz crystal should be connected across these pins. If an external clock source is used, it should be connected to XTAL1 and XTAL2 should be left open. AUI receive differential inputs.
115
nEnable 16 Bit
nEN16
I with pullup
101 102
Crystal 1 Crystal 2
XTAL1 XTAL2
Iclk
123 124 2 3
AUI Receive
RECP RECN
Diff. Input
AUI Transmit
TXP/nCOLL TXN/nCRS
Diff. Output
Internal ENDEC - (nXENDEC pin open). In this mode TXP and TXN are the AUI transmit differential outputs. They must be externally pulled up using 150 ohm resistors. External ENDEC - (nXENDEC pin tied low). In this mode the pins are inputs used for collision and carrier sense functions.
I
15
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 125 126 121 122 4 6 5 7 TPE Transmit TPE Transmit Delayed TPE Receive NAME AUI Collision SYMBOL COLP COLN TPERXP TPERXN TPETXP TPETXN TPETXDP TPETXDN TYPE Diff. Input DESCRIPTION AUI collision differential inputs. A collision is indicated by a 10 MHz signal at this input pair. 10BASE-T receive differential inputs.
Diff. Input
Diff. Output
Internal ENDEC differential outputs.
10BASE-T
transmit
Diff. Output
10BASE-T delayed transmit differential outputs. Used in combination with TPETXP and TPETXN to generate the 10BASE-T transmit pre-distortion. Internal ENDEC - Powerdown input. It keeps the SMC91C95 in powerdown mode when high (open). Must be low for normal operation. Refer to the Powerdown Matrix following for further details.
114
Powerdown
PWRDWN
I with pullup
Transmit Clock 99 nWakeup Enable
TXCLK
External ENDEC - Transmit clock input from external ENDEC I with pullup Input. When pulled down, the device will enable Magic Packet (MP) logic and put the Ethernet function in powerdown mode. The pin assertion will override the state of WAKEUP_EN and PWRDN bits in CTR, Pwrdwn bit in ECSR, and Enable Function bit ECOR. When deasserted, the WAKEUP_EN and PWRDN bits will be changed to (0), Pwrdwn to (0), and Enable Function to (1). Output. Asserted high if nWAKEUP_EN is asserted and a valid Magic Packet (MP) pattern is detected. The pin remains asserted until nWAKEUP_EN is deasserted. A 22 kohm 1% resistor should be connected between this pin and analog ground.
nWAKEUPEN
100
Wakeup
WAKEUP
O4
118
Bias Resistor
RBIAS
Analog Input
16
DESCRIPTION OF PIN FUNCTIONS
PIN NO. 116 NAME nExternal ENDEC SYMBOL nXENDEC TYPE I with pullup DESCRIPTION When tied low the SMC91C95 is configured for external ENDEC. When tied high or left open the SMC91C95 will use its internal encoder/decoder. +5V power supply pins
13, 25, 37, 51, 62, 71, 80, 89, 104 1, 117, 120 19, 30, 44, 58, 67, 75, 84, 94, 112 8, 119, 127
Power
VDD
Analog Power Ground
AVDD
+5V analog power supply pins
VSS
Ground pins
Analog Ground
AVSS
Analog ground pins
BUFFER TYPES O4 O162 O24 OD16 OD24 I/O24 I IS Iclk Output buffer with 2mA source and 4mA sink Output buffer with 2mA source and 16mA sink Output buffer with 12mA source and 24mA sink Open drain buffer with 16mA sink Open drain buffer with 24mA sink Bidirectional buffer with 12mA source and 24mA sink Input buffer with TTL levels Input buffer with Schmitt Trigger Hysteresis Clock input buffer
17
DIAGNOSTIC
SERIAL
EEPROM
20 MHz 4 4
LEDs
CABLE SIDE
SYSTEM BUS
XTAL1 AEN N/C BALE RESET nSBHE nIORD, nIOWR, 3 nMEMR EECS EESK
XTAL2
EEDI
EEDO
IOS0 IOS1 IOS2 nEN16 ENEEP TPETXP TPETXN TPETXDP TPETXDN TPERXP TPERXN
10BASET
SMC91C95
D0-15
TXP TXN RECP RECN COLP COLN
AUI
Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM
A0-19 nROM nIOCS16 IOCHRDY INTR0-3
18
ADDRESS
RBIAS
4
BUFFER
DATA
PROM
nIRQ
PCMCIA CONNECTOR
nCE1 nCE2 nREG nWE A0-A9, A15 nIORD nIOWR SPKROUT STSCHG RESET nIREQ D0-D15 nMRESET MINT nMCS nRESET INT nCS RDY PWDN RINGIN RINGOUTB SPKR
10BASE-T/AUI INTERFACE
PHONE LINE
SMC91C95
MRDY
nIOIS16 nINPACK nWAIT nOE nFWE nFCS MPWDN MRINGIN MRINGOB SPKRIN
MODEM CHIPSET
nWE nOE
nCE
CS,SK,DI,DO
EXTENDED ATTRIBUTE D0-D7 EPROM 2816 A0-X (Optional)
SERIAL EPROM
(ISA-Hy9346) (PCMCIA-Hy93c66)
Figure 2 - SMC91C95 System Block Diagram for Dual Function PCMCIA Card
19
DATA BUS
MODEM INTERFACE
ADDRESS BUS BUS INTERFACE CONTROL
MANAGEMENT
ARBITER
CSMA/CD
ENDEC
AUI
MMU
TWISTED PAIR TRANSCEIVER
10BASE-T
RAM
Figure 3 - SMC91C95 Internal Block Diagram
20
FUNCTIONAL DESCRIPTION
The SMC91C95 consists of an integrated Ethernet controller mapped entirely in I/O space, as well as support for an external Modem controller also mapped in I/O space. In addition, PCMCIA attribute memory space is decoded to interface an external CIS ROM, with configuration registers as per PCMCIA 3.X extensions implemented on-chip in attribute space above the CIS ROM decode area. The PCMCIA Configuration Registers are accessible also in I/O space to allow non-PCMCIA dual function designs. The Ethernet controller function includes a built-in 6kbyte RAM for packet storage. This RAM buffer is accessed by the CPU through two sequential access regions of 3 kbytes each. The RAM access is internally arbitrated by the SMC91C95 and dynamically allocated between transmit and receive packets using 256 byte pages. The Ethernet controller functionality is identical to the SMC91C94 except where indicated otherwise.
Table 1 - Bus Transactions in ISA Mode A0 8 BIT MODE (nEN16=1) (16 BIT=0) 16 BIT MODE otherwise 1 0 0 1 1 X 0 1 0 1 odd byte even byte even byte odd byte odd byte invalid cycle 0 nSBHE X D0-D7 even byte D8-D15 -
21
Table 2 - Bus Transactions in PCMCIA Mode A0 8 BIT MODE ((IOis8=1) + (nEN16=1).(16BIT=0)) 1 X 16 BIT MODE otherwise 0 0 1 X X 16BIT = CONFIGURATION REGISTER bit 7 IOis8 = ECSR register bit 5 nEN16 = pin nEN16 For the modem function, the transactions are similarxcept that the modem is assumed to be 8 bit wide unless (IOis8=0) and (nMIS16=0). NOTE: The IOis8 value should be identical in MCSR and ECSR if both functions are enabled. 8 Bit mode = (IOis8=1)+(nMIS16=1) 0 1 0 0 0 1 1 X X 0 1 1 0 1 odd byte NO CYCLE even byte even byte odd byte odd byte NO CYCLE odd byte 0 nCE1 0 nCE2 X D0-D7 even byte D8-D15 -
22
Table 3 - SMC91C95 Address Spaces SIGNALS USED PCMCIA Attribute Memory PCMCIA Configuration Registers Modem I/O Space Ethernet I/O Space (1) nOE nWE ISA N PCMCI A Y ON-CHIP N (external ROM) Y DEPTH Up to 32k locations, only even bytes are usable 64 locations, only even bytes are usable 8 locations 16 locations WIDTH 8 bits on even addresses
nOE nWE
N
Y
8 bits
nIORD nIOWR nIORD nIOWR
Y Y
Y Y
N Y
8 bit 8 or 16 bits
(1) This space also allows access to the PCMCIA Configuration Register through Banks 4 and 5 (SMC91C95 only). Except for the bus interface, the functional behavior of the SMC91C95 after initial configuration is identical for ISA and PCMCIA modes. The SMC91C95 includes an arbitrated shared memory of 6 kbytes accessed by the CPU. The MMU unit allocates RAM memory to be used for transmit and receive packets, using 256 byte pages. The arbitration is transparent to the CPU in every sense. There is no speed penalty for ISA type of machines due to arbitration. There are no restrictions on what locations can be accessed at any time. RAM accesses as well as MMU requests are arbitrated. The RAM is accessed by mapping it into I/O space for sequential access. Except for the RAM accesses and the MMU request/release commands, I/O accesses are not arbitrated. The I/O space is 16 bits wide. Provisions for 8 bit systems are handled by the bus interface. 23 In the system memory space, up to 64 kbytes are decoded by the SMC91C95 as expansion ROM. The ROM expansion area is 8 bits wide. Device configuration is done using a serial EEPROM, with support for modifications to the EEPROM at installation time. A Flash ROM is supported for PCMCIA attribute memory. The CSMA/CD core implements the 802.3 MAC layer protocol. It has two independent interfaces, the data path and the control path. Both interfaces are 16 bits wide. The control path provides a set of registers used to configure and control the block. These registers are accessible by the CPU through the SMC91C95's I/O space. The data path is of sequential access nature and typically works in one direction at any given time. An internal DMA type of interface connects the data path to the device RAM through the arbiter and MMU. The CSMA/CD data path interface is not accessible to the host CPU.
The internal DMA interface can arbitrate for RAM access and request memory from the MMU when necessary. An encoder/decoder block interfaces the CSMA/CD block on the serial side. The encoder will do the Manchester encoding of the transmit data at 10 Mbps, while the decoder will recover the receive clock and decode received data. Carrier and Collision detection signals are also handled by this block and relayed to the CSMA/CD block. The encoder/decoder block can interface the network through the AUI interface pairs or it can be programmed to use the internal 10BASE-T transceiver and connect to a twisted pair network. The twisted pair interface takes care of the medium dependent signaling for 10BASE-T type of networks. It is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision detection as well as the link integrity test function. The SMC91C95 provides a 16-bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter. RAM memory is managed by the MMU. Byte and word accesses to the RAM are supported. If the system to SRAM bandwidth is insufficient, the SMC91C95 will automatically use its IOCHRDY line for flow control. However, for ISA buses, IOCHRDY will never be negated. BUFFER MEMORY The logical addresses for RAM access are divided into TX area and RX area. Each one of the areas is 1.536 kbytes long and accommodates one maximum size Ethernet packet.
The TX area is seen by the CPU as a window through which packets can be loaded into memory before queuing them in the TX FIFO of packets. The TX area can also be used to examine the transmit completion status after packet transmission. The RX area is associated to the output of the RX FIFO of packets, and is used to access receive packet data and status information. The logical address is specified by loading the address pointer register. The pointer can automatically increment on accesses. All accesses to the RAM are done via I/O space. A bit in the address pointer also specifies if the address refers to the TX or RX area. In the TX area, the host CPU has access to the next transmit packet being prepared for transmission. In the RX area, it has access to the first receive packet not processed by the CPU yet. The FIFO of packets, existing beneath the TX and RX areas, is managed by the MMU. The MMU dynamically allocates and releases memory to be used by the transmit and receive functions. The MMU related parameters for the SMC91C95 are: RAM size Max. number of packets Max. pages per packet Max. number of pages Page size 6 kbytes (internal) 24 6 24 256 bytes
24
PHYSICAL MEMORY RCV BIT POINTER REGISTER 11-BIT LOGICAL ADDRESS RCV VS. TX AREA SELECTION 2K TX AREA MMU TX PACKET NUMBER
PAGE = 256 bytes
RX PACKET NUMBER
2K RX AREA
MMU
FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA
25
PACKET NUMBER REGISTER STATUS COUNT PACKET #A DATA MEMORY
B
CPU SIDE
TX FIFO
STATUS COUNT DATA
A
PACKET #B TO CSMA
C B
TX COMPLETION FIFO
PACKET #C
STATUS COUNT DATA
C
MMU MAPPING
FIFO PORTS REGISTER LINEAR ADDRESS
FIGURE 5 - TRANSMIT QUEUES AND MAPPING
26
MEMORY
FIFO PORTS REGISTER
STATUS COUNT PACKET #D
D
DATA
E
CPU SIDE RX FIFO
STATUS COUNT PACKET #E
D
DATA
E
FROM CSMA
LINEAR ADDRESS
MMU MAPPING
FIGURE 6 - RECEIVE QUEUE AND MAPPING
27
EEPROM
EEPROM INTERFACE DATA BUS
ADDRESS BUS TX FIFO DMA BUS INTERFACE
RX FIFO
ENDEC CSMA/CD
AUI
CONTROL
TX COMPL FIFO
TWISTED PAIR TRANSCEIVER
10BASET
FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH
28
WRITE DATA REG. READ DATA REG. DATA
ARBITER
MMU
ADDRESS BUFFER RAM
PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the TRANSMIT and RECEIVE areas. The first word is reserved for the status word, the next
word is used to specify the total number of bytes, and that in turn is followed by the data area. The data area holds the packet itself, and its length is determined by the byte count. The packet memory format is word oriented.
bit15 RAM OFFSET (DECIMAL) 0 2 4 DATA A R E A RESERVED S TAT U S W O R D BYTE COUNT (always even)
bit0
1536 Max CONTROL BYTE LAST DATA BYTE (if odd)
FIGURE 8 - DATA PACKET FORMAT TRANSMIT PACKET Written by CSMA upon transmit completion (see Status Register). Written by CPU. Written by CPU. Written by CPU to control ODD/EVEN data bytes. RECEIVE PACKET Written by CSMA upon receive completion (see RX Frame Status Word). Written by CSMA. Written by CSMA. Written by CSMA. Also has ODD/EVEN bit.
STATUS WORD
BYTE COUNT DATA AREA CONTROL BYTE
29
BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. DATA AREA - The data area starts at offset 4 of the packet structure and can extend up to 1536 bytes.
The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS, followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The SMC91C95 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the SMC91C95. It is treated transparently as data both for transmit and receive operations. CONTROL BYTE - The CONTROL BYTE always resides on the high byte of the last word. For transmit packets the CONTROL BYTE is written by the CPU as: 0 0 0 0
X
X
ODD
CRC
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted.
CRC - When set, CRC will be appended to the frame. This bit has only meaning if the NOCRC bit in the TCR is set. For receive packets the CONTROL BYTE is written by the controller as: 0 0 0 0
0
1
ODD
0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the number of data bytes is even
and the byte before the CONTROL BYTE should be ignored.
30
RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory. It is not available as a register. HIGH BYTE ALGN ERR BROD CAST BAD CRC ODD FRM TOOLN G TOO SHORT
LOW BYTE 5 4
HASH VALUE 3 2 1 0
MULT CAST
ALGNERR - Frame had alignment error. BRODCAST - Receive frame was broadcast. BADCRC - Frame had CRC error. ODDFRM - This bit when set indicates that the received frame had an odd number of bytes. TOOLNG - The received frame is longer than 802.3 maximum size (1518 bytes on the cable). TOOSHORT - The received frame is shorter than 802.3 minimum size (64 bytes on the cable). ADDRESS ED 00 00 00 00 00 0D 00 00 00 00 00 01 00 00 00 00 00 2F 00 00 00 00 00
HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed up the group address search. The hash value consists of the six most significant bits of the CRC calculated on the Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the hash value select a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected. Examples of the address mapping:
HASH VALUE 5-0 000 000 010 000 100 111 111 111
MULTICAST TABLE BIT MT-0 bit 0 MT-2 bit 0 MT-4 bit 7 MT-7 bit 7
MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set, and the address was a multicast, the
packet will pass address filtering regardless of other filtering criteria.
31
INTERRUPT STRUCTURE The SMC91C95 merges two main interrupt sources into a single interrupt line. One source is the Ethernet interrupt and the other is the modem interrupt. The Ethernet interrupt is conceptually equivalent to the SMC91C92 interrupt line; it is the OR function of all enabled interrupts within the Ethernet core. The modem interrupt is an input pin (MINT). The enabling, reporting and clearing of these two sources is controlled by the ECOR, ECSR, MCOR and MCSR registers. The interrupt
structure is similar for ISA and PCMCIA modes with the following exceptions: a) PCMCIA uses a single interrupt pin (nIREQ) while ISA can use any of four INTR0-INTR3 pins. PCMCIA defaults to Ethernet interrupts disabled (Enable IREQ=0 in ECOR), while ISA defaults to Ethernet interrupts enabled.
b)
The following table summarizes the interrupt merging:
Table 4 - SMC91C95 Interrupt Merging FUNCTION Interrupt Output PCMCIA MODE nIREQ when either function is enabled. When both functions are disabled the nIREQ is used to report the latched value of MRDY. ISA MODE INTR0-INTR3
Ethernet Interrupt Source Modem Interrupt Source Ethernet Interrupt Enable Modem Interrupt Enable Ethernet Interrupt Status Bit Modem Interrupt Status Bit
OR function of all interrupt bits specified in the Interrupt Status Register ANDed with their respective Enable bits. MINT input pin. Enable IREQ bit in ECOR. This bit defaults low in PCMCIA mode. Enable IREQ bit in ECOR. This bit defaults high in ISA mode.
Enable IREQ bit in MCOR. This bit defaults low. Intr bit in ECSR. Intr bit in MCSR.
32
RESET LOGIC
POR nMRESET SRESET MCOR, SOFT RST -
The pins and bits involved in the different reset mechanisms are: RESET Input Pin
Internal circuit activated by Power On Output pin to reset modem Soft Reset bit in ECOR and one SRESET bit for each function. EPH Soft Reset bit in RCR
Table 5 - Reset Functions SAMPLES ISA VS. PCMCIA MODE Yes TRIGGERS EEPROM READ Yes
RESETS THE FOLLOWING FUNCTIONS RESET Pin POR Circuit ECOR Register SRESET Bit All internal logic
ACTIVATES
nMRESET
Generates an internal reset of at least 15 msec, with same effect as the RESET pin The Ethernet controller function and Ethernet PCMCIA Configuration Registers except for the bit itself The Modem controller function and Modem PCMCIA Configuration Registers except for the bit itself The Ethernet Controller itself except for the IA, CONF, and BASE registers. It does not reset any PCMCIA Configuration Register. No No
MCOR Register SRESET Bit
No
No
SOFT RST
No
No
33
POWERDOWN LOGIC The pins and bits involved in powerdown are: 1. 2. 3. 4. 5. 6. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0). Pwrdwn bits in ECSR and MCSR registers One bit for each function Enable Function bits in ECOR and MCOR registers - One bit for each function PWRDN - Ethernet powerdown bit in Control Register. WAKUP_EN - Magic packet receive enable bit in the Control Register nWAKEUP - Pin for Magic Packet receive + Ethernet function powerdown
SMC91C95 Powerdown States: A) The SMC91C95 is Off and no Clock is running B1) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with No Link Pulses for LAN access B2) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with Link active C) The SMC91C95 is completely powered up (With Active LAN or Host Data transfer) 80MA Max, 40MA typ.
Table 6 - Powerdown Functions POWERDOWN ENTERED (A) PWRDWN/ TXCLK Pin When pin is high and reset is inactive Pwrdwn bit in ECSR is high or Enable Function bit in ECOR is low. Pwrdwn bit in MCSR is high or Enable Function bit in MCOR is low. Pwrdwn bit in ECSR is high or Enable Function bit in ECOR is low or PWRDN bit in Control Register is high POWERDOWN EXITED When pin goes low DOES NOT POWER DOWN
POWERS DOWN: Ethernet Function including Link circuitry; Modem Function Ethernet Function plus any analog logic including link logic Modem
(B1) ECOR and ECSR Powerdown Bits
Otherwise, or when function is reset in ISA mode Otherwise; or Ringing from modem chipset
Modem function, Attribute Memory and PCMCIA Configuration Registers access Ethernet function, Attribute Memory and PCMCIA Configuration Registers access Modem Function, Attribute memory and PCMCIA configuration Registers access, Link Logic
(B2) Power State MCOR and MCSR Bits
(B2) Power State WAKUP_EN (Control Register)
Magic Packet received (WAKUP in EPH status)
Ethernet MAC logic (Link is enabled)
34
Table 6 - Powerdown Functions POWERDOWN ENTERED (B2) Power State nWAKEUP (Pin) When pin is low and reset is inactive POWERDOWN EXITED When pin goes high DOES NOT POWER DOWN Modem Function, Attribute memory and PCMCIA configuration Registers access, Link Logic Modem function, Attribute Memory and PCMCIA Configuration Registers access
POWERS DOWN: Ethernet Function (Link logic enabled)
(B2) Power State PWRDN bit in Control Register
When bit is set
Write access to I/O space or reset
Ethernet Function.
PCMCIA Attribute Memory: Address 07FFEh The Attribute Memory is implemented using a combination of interrnal SRAM and external parallel EEPROM, ROM or Flash ROM. The internal SRAM is initialized during power up using the serial EEPROM. This serial EEPROM in PCMCIA mode is used for the CIS (Card Information Structure). If no serial EEPROM is used, the parallel EEPROM must be used. Internal CIS RAM address space is replaced by part of the external parallel EEPROM in this case. In ISA mode, the serial EEPROM is used for configuration and IEEE Node address making it software compatible to the SMC9000 family of Ethernet LAN Controllers. In ISA mode, the EEPROM is optional requiring a minimum size of 64 X 16 bit word addresses. In PCMCIA mode, the minimum serial EEPROM (if used) size can be 64 X 16 up to 256 X 16. This combination of internal and external attribute memory allows the designer to reduce costs by using a serial EEPROM device when using up to 512 bytes of "Card Information" and, if additional memory is needed, an external EEPROM may be used. When the SMC91C95 goes into powerdown 35
mode, the internal CIS data buffer RAM is reinitialized. The SMC91C95 generates the appropriate control lines (nFCS and nFWE) to read and write the Attribute memory, and it tri-states the data bus during external Attribute Memory accesses. Note that the parallel EEPROM is selected for the first 512 byte CIS information also in the absence of the serial EEPROM in PCMCIA mode. Only even locations are used. PCMCIA Configuration Registers: Address 8000-803Eh The PCMCIA Configuration Registers are stored inside the SMC91C95 above the external Attribute Memory address space. These registers are used to configure and control the PCMCIA related functionality of the Ethernet and Modem functions. These registers are eight bits wide and reside on even locations. The SMC91C95 ignores odd accesses to this area (ignore writes, do not drive the bus on reads). This address offset has been changed from prior SMC9000 PCMCIA designs to allow a larger address range for other attribute memory data. This data could be a larger card information structure or a XIP data image.
Internal VS External Attribute Memory Map
The Internal VS External EPROM attribute memory decodes are shown below. This allows the designer to not require an external EPROM device if the single or multi-function PCMCIA card needs less than 512 bytes of configuration information. As can be seen in the map, if 512 bytes of CIS or less is required, the nFCS and nFWE output pins of the
SMC91C95 need not be used (if serial EEPROM is being used). Internal to the SMC91C95, the memory addressing logic will allow byte or word on odd byte address access (A0=1), the SMC91C95 will generate an arbitrary value of zero (0) since the PCMCIA specification states that the high byte of a word access in attribute memory is a don't care. This allows backward compatibility to 8 bit hosts.
Table 7 - Attribute Memory Address Using Serial EEPROM ATTRIBUTE MEMORYADDRESS 0 - 3FEh 400h-7FFEh 8000h - 803Eh X X EXTERNAL EPROM STORE INTERNAL SRAM STORE (512 BYTES) X CONFIGURATION REGISTERS
Table 8 - Attribute Memory Address without Serial EEPROM ATTRIBUTE MEMORYADDRESS 0 - 7FFEh 8000h - 803Eh EXTERNAL EPROM STORE X X INTERNAL SRAM STORE (512 BYTES) CONFIGURATION REGISTERS
36
I/O SPACE (ISA and PCMCIA Mode) In ISA mode, the base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. A4-A15 are compared against the base I/O address for I/O space accesses. In PCMCIA mode nREG (along with nIORD or nIOWR) defines an I/O access regardless of the A4-A15 value. To limit the I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O area is shared by all banks and can be used to change the bank in use. Registers are described using the following convention:
OFFSET HIGH BYTE
NAME
TYPE
SYMBOL
bit 15 X
bit 14 X bit 6 X
bit 13 X bit 5 X
bit 12 X bit 4 X
bit 11 X bit 3 X
bit 10 X bit 2 X
bit 9 X bit 1 X
bit 8 X bit 0 X
LOW BYTE
bit 7 X
OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided the bank select has the appropriate value. The offset specifies the address of the even byte (bits 0-7) or the address of the complete word. The odd byte can be accessed using address (offset + 1).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers; in that case the offset of each one is independently specified. Regardless of the functional description, when the SMC91C95 is in 16 bit mode, all registers can be accessed as words or bytes. The default bit values upon hard reset are highlighted below each register.
37
Table 9 - Internal I/O Space Mapping BANK0 0 TCR BANK1 CONFIG BANK2 MMU COMMAND BANK3 MT0-MT1 BANK4 ECOR (low byte) ECSR (high byte) BANK5 MCOR (low byte) MCSR (high byte) PRR (low byte) EBASE0 (high byte) IOEIR (low byte) MBASE0 (high byte) MBASE1 (low byte) Msize (high byte)
2 4
EPH STATUS RCR
BASE IA0-IA1
PNR ARR FIFO PORTS
MT2-MT3 MT4-MT5
6 8 A C E
COUNTER MIR MCR RESERVED (0) BANK SELECT
IA2-IA3 IA4-IA5 GENERAL PURPOSE CONTROL BANK SELECT
POINTER DATA DATA INTERRUPT BANK SELECT
MT6-MT7 MGMT REVISION ERCV BANK SELECT
EBASE1 (low byte)
38
BANK SELECT REGISTER OFFSET E NAME BANK SELECT REGISTER TYPE READ/WRITE SYMBOL BSR
HIGH BYTE
0 0
0 0
1 1
1 1
0 0
0 0 BS2
1 1 BS1 0
1 1 BS0 0
LOW BYTE X X X X X
0
BS2, BS1, BS0 - Determine the bank presently in use. The BANK SELECT REGISTER is always accessible except in PCMCIA powerdown mode and is used to select the register bank in use. The upper byte always reads as 33h and can be used to help determine the I/O location of the SMC91C95. BS2 0 0 0 0 1 BS1 0 0 1 1 X
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-BS2. The SMC91C95 implements only four banks in ISA mode, therefore, accesses to non-existing banks (BS2=1) are ignored. All six banks are accessible in PCMCIA mode.
BS0 0 1 0 1 X
BANK# 0 1 2 3 None
39
I/O SPACE - BANK0 OFFSET 0 NAME TRANSMIT CONTROL REGISTER TYPE READ/WRITE SYMBOL TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options. HIGH BYTE FDSE 0 LOW BYTE PAD_E N 0 X X X X X EPH LOOP 0 STP SQET 0 FDUPL X 0 MON_ CSN 0 FORCO L 0 X LOOP 0 NOCRC 0 TXENA 0
FDSE - Full Duplex Switched Ethernet. When set, the SMC91C95 is configured for Full Duplex Switched Ethernet, it defaults clear to normal CSMA/CD protocol. In FDSE mode the SMC91C95 transmit and receive processes are fully independent, namely no deferral and no collision detection are implemented. When FDSE is set, FDUPLX is internally assumed high and MON_CSN is assumed low regardless of their actual values. EPH_LOOP - Internal loopback at the EPH block. Does not exercise the encoder decoder. Serial data is looped back when set. Defaults low. NOTE: After exiting the loopback test, an SRESET in the ECOR or the SOFT_RST in the RCR must be set before returning to normal operation. STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error. Does not stop on SQET error and transmits next frame if clear. Defaults low. FDUPLX - When set, it enables full duplex operation. This will cause frames to be received if they pass the address filter regardless of the source for the frame. When clear the node will not receive a frame sourced by itself. Clearing this bit 40
(Normal Operation) in promiscuous mode allows it to not receive its own packet. MON_CSN - When set, the SMC91C95 monitors carrier while transmitting. It must see its own carrier by the end of the preamble. If it is not seen, or if carrier is lost during transmission, the transmitter aborts the frame without CRC and turns itself off. When this bit is clear the transmitter ignores its own carrier. Defaults low. NOCRC - Does not append CRC to transmitted frames when set; allows software to insert the desired CRC. Defaults to zero, namely CRC inserted. PAD_EN - When set, the SMC91C95 will pad transmit frames shorter than 64 bytes with 00. Does not pad frames when reset. FORCOL - When set, the transmitter will force a collision by deliberately not deferring. After the collision, this bit is automatically reset. This bit defaults low to normal operation. NOTE: The LATCOL bit in EPHSR, setting up as a result of FORCOL, will reset TXENA to 0. In order to force another collision, TXENA must be set to 1 again.
LOOP - Local Loopback. When set, transmit frames are internally looped to the receiver after the encoder/decoder. Collision and Carrier Sense are ignored. No data is sent out. Defaults low to normal mode.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared, the SMC91C95 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared.
TRANSMITS AUI FDSE FDUPLX EPH_LOOP LOOP LOOPS AT TO NETWORK X X 1 0 X X X 0 0 0 X 1 1 1 0 1 0 0 0 0 X 1 0 0 0 EPH Block ENDEC Cable 10BASE-T Driver Normal CSMA/CD - No Loopback Full Duplex Switched Ethernet - No loopback and no SQET No No Yes Yes Yes
X
1
1
0
0
Yes
41
I/O SPACE - BANK0 OFFSET 2 NAME EPH STATUS REGISTER TYPE READ ONLY SYMBOL EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status. HIGH BYTE TX UNRN 0 LOW BYTE TX DEFR 0 LINK_ OK 0 LTX BRD 0 RX_ OVRN 0 SQET 0 CTR _ROL 0 16COL 0 EXC _DEF 0 LTX MULT 0 LOST CARR 0 MUL COL 0 LATCOL 0 SNGL COL 0 WAKEU P 0 TX_SU C 0
TXUNRN - Transmit Underrun. Set if underrun occurs, it also clears TXENA bit in TCR. Cleared by setting TXENA high. This bit may only be set if early TX is being used. LINK_OK - State of the 10BASE-T Link Integrity Test. A transition on the value of this bit generates an interrupt when the LE ENABLE bit in the Control Register is set. RX_OVRN - Upon FIFO overrun, the receiver asserts this bit and clears the FIFO. The receiver stays enabled. After a valid preamble has been detected on a subsequent frame, RX_OVRN is deasserted. The RX_OVRN INT bit in the Interrupt Status Register will also be set and stay set until cleared by the CPU. Note that receive overruns could occur only if receive memory allocations fail. CTR_ROL - Counter Roll over. When set one or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register.
EXC_DEF - Excessive deferral. When set last/current transmit was deferred for more than 1518 * 2 byte times. Cleared at the end of every packet sent. LOST_CARR - Lost carrier sense. When set indicates that Carrier Sense was not present at end of preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset. Cleared by setting TXENA bit in TCR. LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting TXENA in TCR. WAKEUP - When this bit is set, it indicates that a receive packet was received that had the "Magic Packet" (MP) signature of the node's own IP address repetitions in it. This bit indicates a valid
42
detection for magic packet - enabled by nWAKEUPEN pin (92 QFP) or WAKEUP_EN in CTR. NOTE: If the MP mode is activated using the nWAKEUPEN pin, the pin must be deasserted to exit the mode. TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 sec of the inter frame gap. Cleared at the end of every packet sent. LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit frame. SQET - Signal Quality Error Test. The transmitter opens a 1.6 sec window 0.8 sec after transmission is completed and the receiver returns inactive. During this window, the transmitter expects to see the SQET signal from the transceiver. The absence of this signal is a 'Signal Quality Error' and is reported in this status bit. Transmission stops and EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit is cleared by setting TXENA high. 16COL- 16 collisions reached. Set when 16 collisions are detected for a transmit frame.
TXENA bit in TCR is reset. Cleared when TXENA is set high. LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit frame. MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced. Cleared when TX_SUC is high at the end of the packet being sent. SNGLCOL - Single collision detected for the last transmit frame. Set when a collision is detected. Cleared when TX_SUC is high at the end of the packet being sent. TX_SUC - Last transmit was successful. Set if transmit completes without a fatal error. This bit is cleared by the start of a new frame transmission or when TXENA is set high. Fatal errors are: 16 collisions SQET fail and STP_SQET = 1 FIFO Underrun Carrier lost and MON_CSN = 1 Late collision
43
I/O SPACE - BANK0 OFFSET 4 NAME RECEIVE CONTROL REGISTER SOFT_ RST 0 LOW BYTE 0 0 0 0 0 FILT_ CAR 0 0 0 0 0 TYPE READ/WRITE SYMBOL RCR
HIGH BYTE
0 0
0 0 ALMUL 0
STRIP_ CRC 0 PRMS 0
RXEN 0 RX_ ABORT 0
SOFT_RST - Software activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The SMC91C95 configuration is not preserved, except for Configuration, Base, and IA0-IA5 Registers. The EEPROM in both ISA and PCMCIA mode is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times. Otherwise recognizes a receive frame as soon as carrier sense is active. STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory following the packet. Defaults low.
RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low on reset. ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear accepts only the multicast frames that match the multicast table setting. Defaults low. PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission unless it is in full duplex. RX_ABORT - This bit is set if a receive frame is aborted due to length longer than 1532 bytes. The frame will not be received. The bit is cleared by RESET or by the CPU writing it low. RX_OVRN_INT 0 1
RX_ABORT Packet Too Long Run out of Memory During Receive 1 1
44
I/O SPACE - BANK0 OFFSET 6 NAME COUNTER REGISTER TYPE READ ONLY SYMBOL ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do not wrap around beyond 15. HIGH BYTE NUMBER OF EXC. DEFFERED TX 0 LOW BYTE 0 0 0 0 0 NUMBER OF DEFFERED TX 0 0 0
MULTIPLE COLLISION COUNT 0 0 0 0
SINGLE COLLISION COUNT 0 0 0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS REGISTER bit description, occurs. Note that the counters can only increment once per enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the counters. For example if a packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented by one. If a packet experiences between 2 to 16 collisions, the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences
deferral the NUMBER OF DEFERRED TX field is incremented by one, even if the packet experienced multiple deferrals during its collision retries. The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts are generated on successful transmissions. Reading the register in the transmit service routine will be enough to maintain statistics.
45
I/O SPACE - BANK0 OFFSET 8 NAME MEMORY INFORMATION REGISTER TYPE READ ONLY SYMBOL MIR
HIGH BYTE 0 LOW BYTE 0 0 0
FREE MEMORY AVAILABLE (IN BYTES * 256 * M) 0 1 1 0 0 0
MEMORY SIZE (IN BYTES *256 * M) 0 1 1 0 0 0
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H (6144 bytes) for the SMC91C95.
MEMORY SIZE REGISTER SMC91C90 SMC91C90 SMC91C92/4 SMC91C95 SMC91C100 FFH 40H 12H 18H FFH
M
ACTUAL MEMORY
1 1 1 1 2
64 kbytes 16 kbytes 4608 bytes 6144 bytes 128 kbytes
46
I/O SPACE - BANK0 OFFSET A NAME MEMORY CONFIGURATION REGISTER TYPE Lower Byte READ/WRITE Upper Byte READ ONLY SYMBOL MCR
HIGH BYTE 0 LOW BYTE 0 0 1 1
MEMORY SIZE MULTIPLIER 0 0 1 1
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M) 0 0 0 0 0 0 0
MEMORY RESERVED FOR TRANSMIT Programming this value allows the host CPU to reserve memory to be used later for transmit, limiting the amount of memory that receive packets can use up. When programmed for zero, the memory allocation between transmit and receive is completely dynamic. When programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free memory is less or equal to the programmed value. This register defaults to zero upon reset. It is not affected by the RESET MMU command. DEVICE FEAST SMC91C90 FUTURE FUTURE FUTURE bit 11 0 0 0 1 1 bit 10 1 0 1 0 0
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with transmit allocations) the CPU should update the value of this register after allocating or releasing memory. The contents of MIR as well as the low byte of MCR are specified in 256 * M bytes. The multiplier M is determined by bits 11,10, and 9 as follows. Bits 11,10 and 9 are read only bits used by the software driver to transparently run on different controllers of the SMC9000 family.
bit 9 0 1 1 0 1
M 2 1 4 8 16
MAX MEMORY SIZE 256*256*2=128k 256*256*1=64k 256k 512k 1M
47
I/O SPACE - BANK1 OFFSET 0 NAME CONFIGURATION REGISTER TYPE READ/WRITE SYMBOL CR
The Configuration Register holds bits that define the device configuration and are not expected to change during run-time. This register is part of the EEPROM saved setup in ISA mode only. In PCMCIA mode, this register is initialized to the state as defined below the corresponding bits as if no EEPROM was present in ISA mode (i.e. ENEEP pin is a don't care in PCMCIA mode). HIGH BYTE 0 NO WAIT X DIS LINK 0 1 X 0 Reserved 1 0 X FULL STEP 0 INT SEL1 0 SET SQLCH 0 INT SEL0 0 X AUI SELEC T 0
0 LOW BYTE 16 BIT Function of EN16 pin
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three 20 MHz clocks on any cycle to the SMC91C95. FULL STEP - This bit is used to select the signaling mode for the AUI port. When set the AUI port uses full step signaling. Defaults low to half step signaling. This bit is only meaningful when AUI SELECT is high. SET SQLCH - When set, the squelch level used for the 10BASE-T receive signal is 240mV. When clear the receive squelch level is 400mV. Defaults low. AUI SELECT - When set the AUI interface is used, when clear the 10BASE-T interface is used. Defaults low.
16BIT - Used in conjunction with nEN16 and IOis8 (in PCMCIA mode only) to define the width of the system bus. If the nEN16 pin is low, this bit is forced high. Otherwise the bit defaults low and can be programmed by the host CPU. DIS LINK - This bit is used to disable the 10BASET link test functions. When this bit is high the SMC91C95 disables link test functions by not generating nor monitoring the network for link pulses. In this mode the SMC91C95 will transmit packets regardless of the link test, the EPHSR LINK_OK bit will be set and the LINK LED will stay on. When low the link test functions are enabled. If the link status indicates FAIL, the EPHSR LINK_OK bit will be low, while transmit packets enqueued will be processed by the SMC91C95, transmit data will not be sent out to the cable. INT SEL1-0 - In ISA mode, used to select one out of four interrupt pins. The three unused interrupts are tristated.
48
INT SEL1
INT SEL0
INTERRUPT PIN USED INTR0 INTR1 INTR2 INTR3
0 0 1 1
0 1 0 1
49
I/O SPACE - BANK1 OFFSET 2 NAME BASE ADDRESS REGISTER TYPE READ/WRITE SYMBOL BAR
For ISA mode only, this register holds the I/O address decode option chosen for the I/O and ROM space. It is part of the EEPROM saved setup, and is not usually modified during run-time. NOTE: This register should ONLY be used in ISA mode. In PCMCIA mode, this register is read only. HIGH BYTE A15 0 LOW BYTE A14 0 A13 0 RA18 1 A9 1 RA17 0 A8 1 RA16 0 A7 0 RA15 1 A6 0 RA14 1 1 A5 0
ROM SIZE 0 1
A15 - A13 and A9 - A5 - These bits are compared in ISA mode against the I/O address on the bus to determine the IOBASE for SMC91C95 registers. The 64k I/O space is fully decoded by the SMC91C95 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros. ROM SIZE - Determines the ROM decode area in ISA mode memory space as follows: 00 = ROM disable 01 = 16k: RA14-18 define ROM select 10 = 32k: RA15-18 define ROM select 11 = 64k: RA16-18 define ROM select RA18-RA14 - These bits are compared in ISA mode against the memory address on the bus to determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are
read only memory accesses defined by nMEMRD going low. For a full decode of the address space unspecified upper address lines have to be: A19 = "1", A20-A23 lines are not directly decoded, however ISA systems will only activate nMEMRD only when A20-A23=0. All bits in this register are loaded from the serial EEPROM in ISA Mode only. In PCMCIA mode, the I/O base is set to the default value (as in ISA mode) as defined below. The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01. ROM decode defaults to CC000 (namely the low byte defaults to 67h).
50
I/O SPACE - BANK1 OFFSET 4 THROUGH 9 NAME INDIVIDUAL ADDRESS REGISTERS TYPE READ/WRITE SYMBOL IAR
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload in ISA mode only. The registers can be modified by the software driver, but a STORE operation will not modify (in ISA mode only) the EEPROM Individual Address contents. In PCMCIA mode, the IEEE Individual Address is stored in the EEPROM, but is stored in PCMCIA Tuple format as defined in the Metaformat specification. Refer to the PCMCIA v3.0 card specification on the Metaformat.
The SMC91C95 in PCMCIA mode knows nothing about the location or structure of the IEEE Ethernet Address stored in the EEPROM. Once this data is stored in the CIS SRAM data buffer in the SMC91C95, it is parsed by the host to extract the IEEE Address information and stored manualy by the LAN Driver. Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable.
HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDRESS 0 0 0 0 0 0
ADDRESS 1 0 0 0 0 0
ADDRESS 2 0 0 0 0 0
ADDRESS 3 0 0 0 0 0
ADDRESS 4 0 0 0 0 0
ADDRESS 5 0 0 0 0 0
51
I/O SPACE - BANK1 OFFSET A HIGH BYTE 0 LOW BYTE 0 0 0 0 0 NAME GENERAL PURPOSE REGISTER TYPE READ/WRITE SYMBOL GPR
HIGH DATA BYTE 0 0 0 0 0
LOW DATA BYTE 0 0 0 0 protected 0 from
This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the software driver. The storage is word oriented, and the EEPROM word address to be read or written is specified using the six lowest bits of the Pointer Register. In PCMCIA mode, Bits 0 to 10 of the pointer register are used. This register can also be used to sequentially program the Individual Address area of the
EEPROM, that is normally accidental Store operations.
This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the SMC91C95.
52
I/O SPACE - BANK1 OFFSET C HIGH BYTE 0 0 LOW BYTE LE ENABLE 0 NAME CONTROL REGISTER RCV_ BAD 0 CR ENABLE 0 PWRDWN WAKEU P_EN 0 TE ENABLE 0 X X 0 TYPE READ/WRITE AUTO RELEASE 0 X EEPROM SELECT 0 X SYMBOL CTR 1 1
RELOAD STORE 0 0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and their memory is released. PWRDN - Active high bit used to put the Ethernet function in powerdown mode. Cleared by: 1. A write to any register in the SMC91C95 I/O space 2. Hardware reset 3. "Magic Packet" was received This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to determine when the function is powered down. WAKUP_EN - Active high bit used to enable the controller in any of the powerdown modes to power up if a "Magic Packet" is detected and set the WAKEUP bit in the EPHSR to generate an EPH interrupt (if not masked). When clear (0), no "Magic Packet" scanning is done on receive packets. NOTE: If "Magic Packet" is enabled using this bit only the notification is done on the WAKEUP bit in the EPHSR only.
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will only generate an interrupt when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The packet number that failed is the present in the FIFO PORTS register, and its pages are not released, allowing the CPU to restart the sequence after corrective action is taken. LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into the EPH INT bit. Defaults low (disabled). Writing this bit also serves as the acknowledge by clearing previous LINK interrupt conditions.
53
CR ENABLE - Counter Roll over Enable. When set it enables the CTR_ROL bit as one of the interrupts merged into the EPH INT bit. Defaults low (disabled). TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit. Defaults low (disabled). Transmit Error is any condition that clears TXENA with TX_SUC staying low as described in the EPHSR register. EEPROM SELECT - This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE refers to. When high, the General Purpose Register is the only register read or written. When low, the RELOAD and STORE functions are enabled. RELOAD In ISA Mode: The SMC91C95 reads the Configuration, Base and Individual Address, and STORE writes the Configuration and Base registers. Also when set it will read the EEPROM and update relevant registers with its contents. This bit then Clears upon completing the operation. In PCMCIA Mode: The SMC91C95 reads the contents of the EEPROM and stores the
contents in the SMC91C95 CIS SRAM as defined in Table 10. STORE In ISA Mode: The STORE bit when set, stores the contents of all relevant registers in the serial EEPROM. This bit is cleard upon completing the operation. In PCMCIA Mode: The SMC91C95 performs no function. NOTE: When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high. The remaining 14 bits of this register will be invalid. During this time, attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the SMC91C95 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 sec. PCMCIA EEPROM to SRAM Memory Map As defined in the PCMCIA specification, Odd byte attribute memory locations are a don't care. In order to utilize the serial EEPROM and internal SMC91C95 SRAM, the data to memory mapping is shown in Table 10.
54
Table 10 - PCMCIA EEPROM to SRAM Memory Map ATTRIBUTE MEMORY ATTRIBUTE EEPROM ADDRESS SMC91C95 SRAM HOST ADDRESS (HEX) DATA IN WORDS IN BYTES 000 Data byte 0 Word 1 - Low Byte Byte 0 001 Don't Care 002 Data byte 1 Word 1 - High Byte Byte1 003 Don't Care 004 Data byte 2 Word 2 - Low Byte Byte2 005 Don't Care 006 Data byte 3 Word 2 - High Byte Byte3 .. .. .. .. 3F8 Data byte 1FC Word FE - Low Byte Byte FC 3F9 Don't Care 3FA Data byte 1FD Word FE- High Byte Byte1FD 3FB Don't Care 3FC Data byte 1FE Word FF - Low Byte Byte1FE 3FD Don't Care 3FE Data byte 1FF Word FF - High Byte Byte1FF 3FF Don't Care NOTE: This memory map assumes a 4096 bit Serial EEPROM in PCMCIA mode.
55
I/O SPACE - BANK2 OFFSET 0 NAME MMU COMMAND REGISTER TYPE WRITE ONLY BUSY Bit Readable SYMBOL MMUCR
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH BYTE
LOW BYTE x
COMMAND y z
0
0
N2
N1
N0/BUS Y
0 COMMAND SET: xyz 000 001 0) 1) NOOP - NO OPERATION ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as (value + 1) * 256 bytes. Namely N2,N1,N0 = 1 will request 2 * 256 = 512 bytes. Valid range for N2,N1,N0 is 0 through 5. A shift-based divide by 256 of the packet length yields the appropriate value to be used as N2,N1,N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. The allocation time can take worst case (N2,N1,N0 + 2) * 200ns. RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet FIFO pointers. REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed processing of present receive frame. This command removes the receive packet number from the RX FIFO and brings the next receive frame (if any) to the RX area (output of RX FIFO). REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by the packet presently at the RX FIFO output. RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER. Should not be used for frames pending transmission. Typically used to remove transmitted frames, after reading their completion status. Can be used following 3) to release receive packet memory in a more flexible way than 4).
010 011
2) 3)
100 101
4) 5)
56
110
6)
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. RESET TX FIFOs - This command will reset both TX FIFOs: the TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory.
111
7)
NOTE 1: Only command 1) uses N2,N1,N0. NOTE 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command. NOTE 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it.
COMMAND SEQUENCING A second allocate command (command 1) should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt. A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing
command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low. BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command.
57
I/O SPACE - BANK2 OFFSET 2 NAME PACKET NUMBER REGISTER TYPE READ/WRITE SYMBOL PNR
PACKET NUMBER AT TX AREA 0 0 0 0 0 0 0 0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this
register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
OFFSET 3
NAME ALLOCATION RESULT REGISTER
TYPE READ ONLY
SYMBOL ARR
This register is updated upon an ALLOCATE MEMORY MMU command. FAILED 1 0 0 0 ALLOCATED PACKET NUMBER 0 0 0 0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence: 1) 2) 3) Allocate Command Poll ALLOC_INT bit until set Read Allocation Result Register
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only valid if the FAILED bit is clear. NOTE: For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits (provided FAILED = 0).
58
I/O SPACE - BANK2 OFFSET 4 NAME FIFO PORTS REGISTER TYPE READ ONLY SYMBOL FIFO
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register. HIGH BYTE REMPT Y 1 LOW BYTE TEMPT Y 1 0 0 0 0 0 0 RX FIFO PACKET NUMBER 0 0 0 0
TX DONE PACKET NUMBER 0 0 0 0
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the Interrupt Status Register. TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4). TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status Register.
TX DONE PACKET NUMBER - Packet number presently at the output of the TX Completion FIFO. Only valid if TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued. NOTE: For software compatibility with future versions, the value read from each FIFO register is intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
59
I/O SPACE - BANK2 OFFSET 6 HIGH BYTE RCV 0 LOW BYTE 0 0 0 NAME POINTER REGISTER AUTO INCR. 0 READ 0 ETEN 0 TYPE READ/WRITE 0 0 0 SYMBOL PTR POINTER HIGH 0 0
POINTER LOW 0 0 0 0 0
POINTER REGISTER -The value of this register determines the address to be accessed within the transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set. The increment is by one for every byte access, and by two for every word access. When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register. READ bit - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high, generates a pre-fetch into the Data Register for read purposes. Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being interrupted.
The Pointer Register should not be loaded until 400ns after the last write operation to the Data Register to ensure that the Data Register FIFO is empty. If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last. ETEN bit - When set enables EARLY Transmit underrun detection. Normal operation when clear. For Underrun detection purposes the RAM logical address and packet numbers of the packet being loaded are compared against the logical address and packet numbers of the packet being transmitted. If the packet numbers match and the logical address of the packet being transmitted exceeds the address being loaded the packet transmission is aborted and Underrun is reported in the transmit status word. NOTE: If AUTO INCR. is not set and 16 bits are used, the pointer must be loaded with an even value. If AUTO INCR. is not set and 8 bit (allows even and odd values) writes are used, consecutive writes to the data register for the same pointer (same memory address) value is not allowed; even and odd pointer values are always allowed.
60
I/O SPACE - BANK2 OFFSET 8 THROUGH Ah NAME DATA REGISTER DATA HIGH TYPE READ/WRITE SYMBOL DATA
DATA LOW
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two uni-directional FIFOs that allow moving words to and from the SMC91C95 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers. The
order to and from the FIFO is preserved. Byte and word accesses can be mixed on the fly in any order. This register is mapped into two consecutive word locations to facilitate the usage of double word move instructions. The DATA register is accessible at any address in the 8 through Ah range, while the number of bytes being transferred are determined by A0 and nSBHE in ISA mode, and by A0, nCE1 and nCE2 in PCMCIA mode.
61
I/O SPACE - BANK2 OFFSET C NAME INTERRUPT STATUS REGISTER ERCV INT X OFFSET C 0 EPH INT RX_OVR N INT 0 TYPE READ ONLY ALLOC INT 0 TX EMPTY INT 1 TYPE WRITE ONLY SYMBOL IST TX INT RCV INT
0
0
0 SYMBOL ACK
NAME INTERRUPT ACKNOWLEDGE REGISTER ERCV INT RX_OVR N INT
TX EMPTY INT
TX INT
OFFSET D
NAME INTERRUPT MASK REGISTER ERCV INT EPH INT RX_OVR N INT 0
TYPE READ/WRITE ALLOC INT 0 TX EMPTY INT 0
SYMBOL MSK TX INT RCV INT
X
0
0
0
0
This register can be read and written as a word or as two individual bytes. The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. An enabled bit being set will cause a hardware interrupt. EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), 62
and enabling of these sources can be done via the Control Register. The possible sources are: LINK_OK transition CTR_ROL - Statistics counter roll over. TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits: TXUNRN - Transmit underrun SQET - SQE Error LOST CARR - Lost Carrier LATCOL - Late Collision 16COL - 16 collisions
WAKE_UP - "Magic Packet" is received if enabled RX_OVRN INT - Set when the receiver overruns due to a failed memory allocation. The RX_OVRN bit of the EPHSR will also be set, but if a new packet is received it will be cleared. The RX_OVRN INT bit, however, latches the overrun condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set. ALLOC INT - Set when an MMU request for TX pages allocation is completed. This bit is the complement of the FAILED bit in the ALLOCATION RESULT register. The ALLOC INT ENABLE bit should only be set following an allocation command, and cleared upon servicing the interrupt. TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is desired, the bit should be first cleared and then read. The TX EMPTY INT ENABLE should only be set after the following steps: a) b) a packet is enqueued for transmission the previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed. The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit set. RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch). ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the ERCV INT bit set. NOTE: If the driver uses AUTO RELEASE mode it should enable TX EMPTY INT as well as TX INT. TX EMPTY INT will be set when the complete sequence of packets is transmitted. TX INT will be set if the sequence stops due to a fatal error on any of the packets in the sequence. NOTE: For edge triggered systems, the Interrupt Service Routine should clear the Interrupt Mask Register, and only enable the appropriate interrupts after the interrupt source is serviced (acknowledged).
63
RCV FIFO NOT EMPTY RCV INT
TX FIFO EMPTY TX COMPLETION FIFO NOT EMPTY TX INT
D2 D nWRACK nQ
INT
SQ
TX EMPTY INT
ALLOCATION FAILED RX_OVRN (EPHSR)
ALLOC INT
RX_OVRN INT D4 D nQ SQ EPH INT
FIGURE 9 - INTERRUPT STRUCTURE
EDGE DETECTOR ON LINK ERR LEMASK CTR-ROL CRMASK TEMASK 5 4 3 2 1 INTERRUPT TXENA TX_SVC nRDIST OE D0-7 EPHSR INTERRUPTS MERGED INTO EPH INT DATA BUS 16 STATUS REGISTER 0 5
64
MAIN INTERRUPTS
4
3
2
1 INTERRUPT MASK REGISTER
0 nOE
D8-15
I/O SPACE - BANK 3 OFFSET 0 THROUGH 7 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NAME MULTICAST TABLE TYPE READ/WRITE SYMBOL MT
MULTICAST TABLE 0 0 0 0 0 0
MULTICAST TABLE 1 0 0 0 0 0
MULTICAST TABLE 2 0 0 0 0 0
MULTICAST TABLE 3 0 0 0 0 0
MULTICAST TABLE 4 0 0 0 0 0
MULTICAST TABLE 5 0 0 0 0 0
MULTICAST TABLE 6 0 0 0 0 0
MULTICAST TABLE 7 0 0 0 0 0
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of the CRC of the destination addresses. The three msb's determine the register to be used (MT0-MT7), while the other three determine the bit within the register. If the appropriate bit in the table is set, the packet is received. If the ALMUL bit in the RCR register is
set, all multicast addresses are received regardless of the multicast table values. Hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive status word, the receive routine can reduce the search time significantly. With the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question.
65
I/O SPACE - BANK3 OFFSET 8 HIGH BYTE 0 LOW BYTE 0 0 1 1 0 1 1 MDOE 0 MCLK 0 MDI 0 MDO 0 NAME MANAGEMENT INTERFACE TYPE READ/WRITE nXNDE C IOS2 SYMBOL MGMT IOS1 IOS0
nXNDEC - Read only bit reflecting the status of the nXENDEC pin. IOS0-IOS2 - Read only bits reflecting the status of the IOS0-IOS2 pins. MDO - The value of this bit drives the EEDO pin when MDOE=1.
MDI - Reads the value of the EEDI pin. MDCLK - The value of this bit drives the EESK pin when MDOE=1. MDOE - When this bit is high pins EEDO EECS and EESK will be used for transceiver management functions, otherwise the pins assume the EEPROM values. MDOE=1 Bit MDO Bit MCLK 0
MDOE=0 EEDO EESK EECS Serial EEPROM Data Out Serial EEPROM Clock Serial EEPROM Chip Select
66
I/O SPACE - BANK3 OFFSET A HIGH BYTE 0 LOW BYTE 0 1 0 CHIP 0 0 0 0 1 1 0 0 REV 0 0 1 1 NAME REVISION REGISTER TYPE READ ONLY SYMBOL REV
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
CHIP ID VALUE 3 4 5 7
DEVICE SMC91C90/SMC91C92 SMC91C94 SMC91C95 FEAST
67
I/O SPACE - BANK 3 OFFSET C HIGH BYTE 0 LOW BYTE RCV DISCR D 0 0 0 1 1 0 1 1 0 0 ERCV THRESHOLD 1 1 NAME EARLY RCV REGISTER TYPE READ/WRITE SYMBOL ERCV
1
1
1
RCV DISCRD - Set to discard a packet being received. This bit can be used in conjunction with ERCV THRESHOLD and ERCV INT to process a packet header while it is being received and sicard it if the packet is not desired. Setting this bit will only discard packets that are still in the process of being received. If the RCV DISCRD bit is set prior to the end of a receive packet, RXOVRN bit in the Interrupt Status Register will be set to indicate that the packet was discarded and its memory released. If the receive
packet is complete prior to the RCV DISCRD bit being set, the packet is received normally and RCV INT bit is set in the Interrupt Status Register. The RCV DISCRD bit is self-clearing. ERCV THRESHOLD - Threshold for ERCV interrupt. Specified in 64 byte multiples. Whenever the number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT bit of the INTERRUPT STATUS REGISTER is set.
68
THEORY OF OPERATION
PC Card 5.0 treats the individual functions of a multifunction PCMCIA application independently. Card and Socket Services (C&SS) 5.0 is designed to provide the support for determining the function generating the interrupt and informing relevant drivers. The registers for the two functions are treated as independent sets. One of the only requirements is to set the functions' I/O base registers with different values to avoid any access conflict. MEMORY ARCHITECTURE The concept of presenting the shared RAM as FIFO of packets, with a memory management unit allocating memory on a per packet basis responds to the following needs: Memory allocation for receive vs. transmit - A fixed partition between receive and transmit area would not be efficient. Being able to dynamically allocate it to transmit and receive represents almost the equivalent of duplicating the memory size for some workstation type of drivers. Software overhead - By presenting a FIFO of packets, the software driver does not have to waste any time in calculating pointers for the different buffers that make up different packets. The driver usually deals with one packet at a time. With this approach, packets are accessible always at the same fixed address, and access is provided to any byte of the packet. Headers can be analyzed without reading out the entire packet. The packet can be moved in or out with a block move operation. Multiple upper layer support - The SMC91C95 facilitates interfacing to multiple upper layer protocols because of the receive packet Efficiency - Lacking any level of indirection or linked lists of pointers, virtually all the memory is used for data. There are not descriptors, forward links and pointers at all. This simplicity and memory efficiency is accomplished without giving up the benefits of linked lists which is unlimited back-to-back transmission and reception without CPU intervention for as long as memory is available. FULL DUPLEX ETHERNET SUPPORT Full Duplex Ethernet operation refers to the ability of the network (or parts of it) to simultaneously transmit and receive packets. The CSMA/CD protocol used by Ethernet for accessing a shared medium is inherently half duplex , and so is the 10BASE-T physical layer where simultaneous transmit and receive activity is interpreted as a collision. The SMC91C95 supports two types of Full Duplex operation: 1. Full Duplex mode for diagnostic purposes only, where the received packet is the transmit packet being looped back. This mode is enabled using the FDUPLX bit in the TCR. In this mode the CSMA/CD algorithm is used to gain access to the media. processing flexibility. A receive lookahead scheme like ODI or NDIS drivers is supported by copying a small part of the received packet and letting the upper layer provide a pointer for the rest of the data. If the upper layer indicates it does not want a specific part of the packet, a block move operation starting at any particular offset can be done. Out of order receive processing is also supported: if memory for one packet is not yet available, receive packet processing can continue.
69
2.
FDSE (Full Duplex Switched Ethernet). Enabled by FDSE bit in TCR bit. When the SMC91C95 is configured for FDSE, its transmit and receive paths will operate independently and some CSMA/CD functions are disabled such as Carrier Sense.
T front end, AUI front end, or External Endec interface. This collision input is observed by the Transmit State Machine while `transmitting' is true, that is during Preamble, Data, Pad, and CRC states. If collision is active during any of these states the state machine transitions to JAM and BACKOFF states. 3. 10BASE-T loopback - Typically 10BASE-T drivers are internally looped back to the differential receivers.
Behavior in FDSE Mode The main 802.3 section affected by FDSE is 4.2.8 where the Frame Transmission procedural model is presented. The changes are: 1. No deferral - The transmit channel is dedicated and always available - The device will transmit whenever it has a packet ready to be sent, while respecting the interframe spacing between transmit packets. No collision detection - There are no collisions in a switched environment. The EPH implementation of the procedural model uses as `collisionDetect' the MAC collision input, sourced from the 10BASE-
"Magic Packet" Support
If the WAKEUP_EN bit in the Control Register (Bank1, Offset C) is set, the controller will come out of any powerdown mode. If this bit is not set, this functionality is disabled. When a "Magic Packet" is received, the ethernet controller will generate an interrupt causing the host to initiate a service routine to find the source of the event. The Interrupt bit in the ECSR is also set if the host plans on polling the controller for Wakeup status.
2.
70
TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES - the MMU attempts to allocate N bytes of RAM. WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt. The TX packet number is now at the Allocation Result Register. LOAD TRANSMIT DATA - Copy the TX packet number into the Packet Number Register. Write the Pointer Register, then use a block move operation from the upper layer transmit queue into the Data Register. ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO" - This command writes the number present in the Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. The enqueued packet will be transferred to the CSMA/CD block as a function of TXENA (n TCR) bit and of the deferral process (in half duplex mode) state. Upon transmit completion the first word in memory is written with the status word. The packet number is moved from the TX FIFO into the TX completion FIFO. Interrupt is generated by the TX completion FIFO being not empty. SERVICE INTERRUPT - Read Interrupt Status Register. If it is a transmit interrupt, read the TX Done Packet Number from the FIFO Ports Register. Write the packet number into the Packet Number Register. The corresponding status word is now readable from memory. If status word shows successful transmission, issue RELEASE packet number command to free up the memory used by this packet. Remove packet number from completion FIFO by writing TX INT Acknowledge Register. CSMA/CD SIDE
2
3
4
5
6
7
71
TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 2 ENABLE RECEPTION - By setting the RXEN bit. A packet is received with matching address. Memory is requested from MMU. A packet number is assigned to it. Additional memory is requested if more pages are needed. The internal DMA logic generates sequential addresses and writes the receive words into memory. The MMU does the sequential to physical address translation. If overrun, packet is dropped and memory is released. When the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. Byte count is placed at the second word. If the CRC checks correctly the packet number is written into the RX FIFO. The RX FIFO being not empty causes RCV INT (interrupt) to be set. If CRC is incorrect the packet memory is released and no interrupt will occur. SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet is at receive area. (Its packet number can be read from the FIFO Ports Register). The software driver can process the packet by accessing the RX area, and can move it out to system memory if desired. When processing is complete the CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. CSMA/CD SIDE
3
4
5
72
ISR
Save Bank Select & Address Ptr Registers
Mask 91C94 Interrupts
Read Interrupt Register
No RX INTR? Y es Call TX INTR or TXEMPTY INTR TX INTR? No
Y es
Call RXINTR
Get Next TX
Y es
Packet Available for Transmission?
ALLOC INTR? No No Y es Write Allocated Pkt # into Packet Number Reg. Write Ad Ptr Reg. & Copy Data & Source Address
Call ALLOCATE
Enqueue Packet EPH INTR? Y es Call EPH INTR No Restore Address Pointer & Bank Select Registers Set "Ready for Packet" Flag
Return Buffers to Upper Layer
Unmask 91C94 Interrupts
Disable Allocation Interrupt Mask
Exit ISR
FIGURE 10 - ETHERNET INTERRUPT SERVICE ROUTINE
73
INTERRUPT 'NOT EMPTY' STATUS REGISTER RCV PACKET NUMBER REGISTER INT RX FIFO PACKET NUMBER
TWO OPTIONS TX INT ALLOC INT 'EMPTY'
TX EMPTY INT
TX FIFO
RX FIFO
RX PACKET NUMBER
TX COMPLETIO N FIFO 'NOT EMPTY'
TX DONE PACKET NUMBER CPU ADDRESS
CSMA ADDRESS
FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
LOGICAL ADDRESS PACKET #
74
M.S. BIT ONLY
CSMA/CD
MMU
PACK # OUT
PHYSICAL ADDRESS
RAM
RX INTR
Write Ad. Ptr. Reg. & Read Word 0 from RAM
Yes
Destination Multicast?
No
Read Words 2, 3, 4 from RAM for Address Filtering
No
Address Filtering Pass?
Yes
No
Status Word OK?
Yes
Do Receive Lookahead
Get Copy Specs from Upper Layer
No
Okay to Copy?
Yes
Copy Data Per Upper Layer Specs
Issue "Remove and Release" Command
Return to ISR
FIGURE 12 - RX INTR 75
TX INTR
Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register
Read Status Word from RAM
Yes
TX Status OK?
No
Update Statistics
Re-Enable TXENA
Immediately Issue "Release" Command
Update Variables
Acknowledge TXINTR
Read TX INT Again
No
TX INT = 0? Yes Restore Packet Number
Return to ISR
FIGURE 13 - TX INTR (Assumes Auto Release Option Selected)
76
TXEMPTY INTR
Write Acknowledge Reg. with TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 0 & TXINT = 0 (Waiting for Completion)
TXEMPTY = X & TXINT = 1 (Transmission Failed)
TXEMPTY = 1 & TXINT = 0 (Everything went through successfully)
Read Pkt. # Register & Save
Write Address Pointer Register
Read Status Word from RAM
Update Statistics
Issue "Release" Command
Update Variables
Acknowledge TXINTR
Re-Enable TXENA
Restore Packet Number
Return to ISR
FIGURE 14 - TXEMPTY INTR 77
DRIVER SEND
ALLOCATE
Choose Bank Select Register 2
Issue "Allocate Memory" Command to MMU
Call ALLOCATE
Read Interrupt Status Register
Exit Driver Send
Yes Read Allocation Result Register Write Allocated Packet into Packet # Register Write Address Pointer Register
Allocation Passed?
No
Store Data Buffer Pointer
Clear "Ready for Packet" Flag
Copy Part of TX Data Packet into RAM
Enable Allocation Interrupt
Write Source Address into Proper Location
Copy Remaining TX Data Packet into RAM
Enqueue Packet
Set "Ready for Packet" Flag
Return Buffers to Upper Layer
Return
FIGURE 15 - DRIVER SEND AND ALLOCATE ROUTINES
78
MEMORY PARTITIONING Unlike other controllers, the SMC91C95 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation. Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the CSMA/CD for receive. The CPU can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive process is going to demand. Furthermore, the receive process requests will be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer software flow control. In order to prevent unwanted traffic from using too much memory, the CPU can program a "memory reserved for transmit" parameter. If the free memory falls below the "memory reserved for transmit" value, MMU requests from the CSMA/CD block will fail and the packets will overrun and be ignored. Whenever enough memory is released, packets can be received again. If the reserved value is too large, the node might lose data which is an abnormal condition. If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the SMC91C95, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory). Whenever the driver 79
needs to burst transmissions it can reduce the receive memory allocation. The driver program the parameter as a function of the following variables: 1) 2) Free memory (read only register) Memory size (read only register)
The reserved memory value can be changed on the fly. If the MEMORY RESERVED FOR TX value is increased above the FREE MEMORY, receive packets in progress are still received, but no new packets are accepted until the FREE MEMORY increases above the MEMORY RESERVED value. INTERRUPT GENERATION The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller. For that purpose there is no register reading necessary before the next element in the queue (namely transmit or receive packet) can be handled by the controller. The transmit and receive results are placed in memory. The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and receive interrupts are enabled. This allows the interrupt service routine to process many receive packets without exiting, or one at a time if the ISR just returns after processing and removing one. There are two types of transmit interrupt strategies: 1) One interrupt per packet 2) One interrupt per sequence of packets The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used.
TX INT bit - Set whenever the TX completion FIFO is not empty. TX EMPTY INT bit - Set whenever the TX FIFO is empty. AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their memory is released automatically. 1) One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the completion result in memory and process the interrupt one packet at a time. Depending on the completion code the driver will take different actions. Note that the transmit process is working in parallel and other transmissions might be taking place. The SMC91C95 is virtually queuing the packet numbers and their status words. In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX DONE PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the SMC91C95 and provided back to the CPU as their transmission completes. 2) One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY INT is generated only after transmitting the last packet in the FIFO. TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore the FIFO will not be emptied. This mode has the advantage of a smaller CPU overhead, and faster memory deallocation. Note that when AUTO RELEASE=1 80
the CPU is not provided with the packet numbers that completed successfully. NOTE: The pointer register is shared by any process accessing the SMC91C95 memory. In order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt. Typically there would be three processes using the pointer: 1) 2) 3) Transmit loading (sometimes interrupt driven) Receive unloading (interrupt driven) Transmit Status reading (interrupt driven)
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines. INTERNAL VS. EXTERNAL ATTRIBUTE MEMORY MAP The Internal vs. External EPROM attribute memory decodes are shown in Table 11 and Table 12. This allows the designer to not require an external EPROM device if the single or multifunction PCMCIA card needs less than 512 bytes of configuration information. As can be seen in the map, if 512 bytes of CIS or less is required, the nFCS and nFWE output pins of the SMC91C95 need not be used (if serial EEPROM is being used). Internal to the SMC91C95, the memory addressing logic will allow byte or word access on even byte boundaries. This implies that on odd byte address access (A0=1), the SMC91C95 will generate a arbitrary value of Zero (0) since the PCMCIA specification states that the high byte of a word access in attribute memory is a don't care. This allows backward compatibility to 8 bit hosts.
Table 11 - Attribute Memory Decodes Using Serial EPROM ATTRIBUTE MEMORYADDRESS 0 - 3FEh 400h-7FFEh 8000h - 803Eh X X EXTERNAL EPROM STORE INTERNAL SRAM STORE (512 BYTES) X CONFIGURATION REGISTERS
Table 12 - Attribute Memory Decodes without Serial EPROM ATTRIBUTE MEMORYADDRESS 0 - 7FFEh 8000h - 803Eh EXTERNAL EPROM STORE X X INTERNAL SRAM STORE (512 BYTES) CONFIGURATIO N REGISTERS
81
PCMCIA CONFIGURATION REGISTERS DESCRIPTION
Ethernet Function (Base Address 8000h) 8000h - Ethernet Configuration Option Register (ECOR)
7 SRESET
6 LevIREQ
5
4
3 WRATTRI B
2 Enable IREQ
1 Enable Base and Limit 0
0 Enable Function
0
1
0
0
0
0
0
BIT 7 - SRESET: This bit when set will clear all internal registers associated with the Ethernet function except itself. BIT 6 - LevIREQ: This bit is read only and reads as a one to indicate level mode interrupts are used. Pulse mode interrupts are not supported. BIT 5 - Not defined BIT 4 - Not defined BIT 3 - WRATTRIB: This bit when when set (1), allows writting into the external attribute memory space. BIT 2 - Enable IREQ Routing: This bit enables (1) or disables (0) the Ethernet function from asserting nIREQ. The nIREQ pin on power up and RESET is in a high (1) de-asserted state. BIT 1 - Enable Base and Limit: This bit enables the on board I/O base decoder. If set, the on-
board decoder is used to select the function. If cleared, the decoder is disabled and it is assumed that the host provides for the decoding. When the decode is disabled, the function is enabled, and is configured for 16 bits (and not in power-down mode), the signal IOIs16 is always asserted. It is then up to the host to qualify the usage of -IOIs16. For multifunction PCMCIA functionality, this bit must be set. BIT 0 - Enable Function: This bit enables (1) or disables (0) the Ethernet function. While the Ethernet function is disabled it remains in powerdown mode, no access to the Ethernet I/O space (ie. The bank register are not accessable) is allowed. IREQ is not generated for this function and nINPACK is not returned for accesses to the Ethernet registers. If the "Magic Packet" function is enabled, the device is not completly powered down. The MAC controller is still enabled to receive.
82
8002h - Ethernet Configuration and Status Register (ECSR) 7 6 5 IOIs8 0 0 0 0 0 4 3 2 Pwrdwn 0 1 Intr 0 0 IntrACK 0
BIT 7 - Not defined BIT 6 - Not defined BIT 5 - IOIs8: This bit when set, indicates that the Host can only do 8 bit cycles (on D7-D0). The Ethernet function is forced in this case to eight bit mode regardless of the nEN16 pin and 16BIT value. This bit also disables (floats) the IOIs16 signal. BIT 4 - Not defined BIT 3 - Not defined
When this bit and Enable IREQ Routing are set, -IREQOut is asserted. All setting and resetting of this bit is edge triggered with exception of the internally generated reset signal for the modem / Ethernet related PC card registers. The Intr bit can be reset the following ways and priority ranging from 1=highest to 3=lowest: 1) 2) A hardware reset/power up The function ie. interrupt source can only reset this field to zero (0) if the IntrACK field is reset to zero (0) The host system can only reset this field to a zero (0) only if the IntrACK bit is set to a one (1)
3) BIT 2 - PwrDwn: When set (1), this bit puts the SMC91C95 Ethernet function into powerdown mode. The Ethernet function is also put into powerdown mode when the Enable Function bit (ECOR bit 0) is cleared. Refer to the Powerdown Logic section for additional details as to what logic is powered down. BIT 1 - Intr: This bit is read/set to a one when this function is requesting interrupt service. It is cleared depending upon the setting of IntrACK.
BIT 0 - IntrACK: This bit controls the clearing of the Intr bit. When this bit is cleared, Intr reflects the function's interrupt status. When this bit is set, the Intr bit must be cleared by the host writing a 0 into it. If the function requires additional service the Intr bit will remain asserted when the host writes the 0.
83
I/O Base Register 0 & 1 (I/O Base 0 & 1) Address 800Ah & 800Ch 800Ah - Ethernet I/O BASE Register 0 7 A7 0 6 A6 0 5 A5 0 4 A4 0 3 0 0 2 0 0 1 0 0 0 0 0
800Ch - Ethernet I/O BASE Register 1 7 A15 0 6 A14 0 5 A13 0 4 A12 0 3 A11 0 2 A10 0 1 A9 1 0 A8 1
The I/O Base registers determine the base address of the I/O range used to access function specific registers. These registers allow the function's registers to be placed anywhere in the host's I/O space. I/O Base 0 contains the low order byte (A7-A0) and I/O Base 1 contains the high order byte (A15-A8). Since the Ethernet function requires 16 I/O locations, bits 3-0 of I/O Base 0 are always 0.
Since only A15 to A4 are decoded by the controller (64K address space), it is up to the host to resolve any conflicts with addressing above 64K. The default decode value is 300h (A9=A8=1, others=0). NOTE: These registers are ignored in ISA mode. These registers are still accessable even if the "Enable Base and Limit) bit in the MCOR is cleared (0).
84
Modem Function (Base Address 8020h) 8020h - Modem Configuration Option Register (MCOR) 7 SRESET 6 LevIREQ 5 4 3 2 Enable IREQ 1 Enable Base and Limit 0 0 Enable Function
0
1
0
0
0
0
0
BIT 7 - SRESET: This bit when set clears all internal registers associated with the Modem function (except itself) and asserts the nMRESET pin . BIT 6 - LevIREQ: This bit is read only and reads as a one to indicate level mode interrupts are used. Pulse mode interrupts are not supported. BIT 5 - Not defined BIT 4 - Not defined BIT 3 - Not defined BIT 2 - Enable IREQ Routing: This bit enables (1) or disables (0) the Modem function from asserting nIREQ.
BIT 1 - Enable Base and Limit: This bit enables the on board modem I/O base decoder. If set, the on-board decoder is used to select the function. If cleared, the decoder is disabled and it is assumed that the host provides for the decoding. When the decode is disabled, the function is enabled, and is configured for 16 bits (and not in power-down mode), the signal IOIs16 is always asserted. For multifunction PCMCIA functionality, this bit must be set. BIT 0 - Enable Function: This bit enables (1) or disables (0) the Modem function. While the Modem is disabled the SMC91C95 inhibits nMCS, IREQ is not generated for the Modem function and nINPACK is not returned for accesses to the Modem registers.
85
8022h - Modem Configuration and Status Register (MCSR) Address 8022h 7 Changed 0 6 SigChg 0 5 IOIs8 0 4 Reserved 0 3 Audio 0 2 Pwrdwn 0 1 Intr 0 0 IntrACK 0
Bit 7 - Changed: This bit is the logical OR of the CREADY/-Bsy and (RINGEVENT bit logically anded with RINGENABLE) states. Bit 6 - SigChg: If this bit is a one, the function is enabled (configured), the Changed bit controls the nSTSCHG pin. If this bit is low or the function is disabled, the nSTSCHG pin is set to a high. Bit 5 - IOIs8: This bit when set, indicates that the Host can only do 8 bit cycles (on D7-D0). In the case of the IOIs8 bit being cleared (0), during Reset and Power up for example, the PIN MIS16 will override the IOIs8 default, setting the bit (1). Bit 4 - ResurvedBit 3 - Audio: This bit controls the audio pass through of the digital audio. When cleared, the SPKROUT pin is three-stated. When set, the SPKRIN pin is passed to the SPKROUT pin. Bit 2 - PwrDwn: When set (1), this bit puts the modem into powerdown mode. The modem is also put into powerdown mode when the Enable Function bit is cleared. When in powerdown, the MRINGIN signal is blocked from going to the ringing output signal. When taken out of powerdown (when PwrDwn is cleared (1) and Enable Function in the MCOR (bit 0) is set (1)), the modem is awakened by a
pulse on the output ringing signals as appropriate. The pulse duration is determined by the input signal MRINGIN. MRINGIN is then passed to the outputs. Bit 1 - Intr: This bit is read/set to a one when this function is requesting interrupt service. It is cleared depending upon the setting of IntrACK. When this bit and Enable IREQ Routing are set, -IREQOut is asserted. The Intr bit can be reset the following ways and priority ranging from 1=highest to 3=lowest: 1) 2) A hardware reset/power up The function ie. interrupt source can only reset this field to zero (0) if the IntrACK field is reset to zero (0). The host system can only reset this field to a zero (0) only if the IntrACK bit is set to a one (1).
3)
Bit 0 - IntrACK: This bit controls the clearing of the Intr bit. When this bit is cleared, Intr reflects the function's interrupt status. When this bit is set, the Intr bit must be cleared by the host writing a 0 into it. If the function requires additional service (indicated by leaving MINT active) the Intr bit will remain asserted when the host writes the 0.
86
8024h - Pin Replacement Register (PRR) 7 6 5 Cready/Bsy 0 0 0 0 0 0 4 3 2 1 Rready/Bsy 1 0 0
Cready/-Bsy: This bit is set to a one when the bit Rready/-Bsy bit changes state from zero(0) to one(1) or one(1) to zero(0) with the source of the change of state is a change in the modem ready (MRDY) signal. The Cready/-Bsy bit can be written by the CPU also. The CPU attempt to write to this bit is masked by the
value for Rready/Bsy bit. A CPU write to this bit is successful only if the Rready/-Bsy bit is being written as one(1). Note that the h/w represented value of the Rready/-Bsy bit itself is not affected by the write attempt as shown in the following illustration:
CURRENT VALUE Cready/-Bsy 0 X X X Rready/-Bsy 0 0 0 1
VALUE WRITTEN Cready/-Bsy 1 1 0 1 Rready/-Bsy 0 1 1 1
NEW VALUE Cready/-Bsy 0 1 0 1 Rready/Bsy 0 0 0 1
In the unlikely event that the MRDY changes state at the same time that the nWE signal changes from low to high (ie. writing the register), the value written by the host will have priority over the new state of the MRDY input pin.
Rready/-Bsy: When read, this bit represents the current state of the modem Ready/-Busy (MRDY) signal. Attempts of CPU writes to this bit are ignored.
87
8028h - Extended Status Register(ESR) 7 6 5 4 RINGEVENT 0 0 0 0 0 0 0 3 2 1 0 RINGENABLE 0
RINGEVENT: This bit is latched to a one at the start of each ring frequency cycle (input from ring input from modem, the MRINGIN signal going high). When this bit and RINGENABLE are both set to a one (1), the Changed bit in the MCSR is set to a one(1). This bit is reset if the
host writes a one (1) and the change bit in the MCSR register is unaffected if the host writes a zero (0). RINGENABLE: When set, this bit gates the RINGEVENT into the Changed bit.
88
802Ah - Modem I/O BASE Register 0 7 A7 0 6 A6 0 5 A5 0 4 A4 0 3 A3 0 2 0 0 1 0 0 0 0 0
802Ch - Modem I/O BASE Register 1 7 A15 0 6 A14 0 5 A13 0 4 A12 0 3 A11 0 2 A10 0 1 A9 1 0 A8 1
The Modem I/O Base registers determine the base address of the I/O range used to access function specific registers. These registers allow the function's registers to be placed anywhere in the host's I/O space. I/O Base 0 contains the low order byte (A7-A0) and I/O Base 1 contains the high order byte (A15-A8). Since the modem function requires 8 I/O locations, bits 2-0 of I/O
Base 0 are always 0. Since only A15 to A4 are decoded by the controller (64K address space), it is up to the host to resolve any conflicts with addressing above 64K. These registers are still accessable even if the "Enable Base and Limit" bit in the MCOR is cleared (0).
89
8032h - Modem I/O Size Register Modem I/O Size Mask 0 0 0 0 0 1 1 1
The I/O Size Register holds a bit mask used to specify the number of address lines decoded by the Modem function. Each bit in the register represents an I/O address line. A value of one means that the SMC91C95 will not decode the corresponding address line for the Modem function, a value of zero means that the address line will be decoded. If a bit in the register is set to one, all bits of lesser significance in the register must also be set to one. This register defaults to 7h, that is A0, A1 and A2 are not decoded resulting in 8 address locations for the modem function. Modem I/O Space: Address determined by Modem I/O Base Registers The Modem I/O space is external to the SMC91C95. The SMC91C95 decodes the address bus ( A15 through A3) via a internal comparator and generates nMCS for I/O cycles that decode to the Modem area as defined by the Modem I/O Base Registers. The I/O address space consists of eight (8) 8-bit locations. The
SMC91C95 will tri-state the data bus during Modem I/O space accesses. In ISA mode, nMCS is disabled (1). No address decodeing for the modem will be done. Ethernet I/O Space: Address determined by Ethernet I/O Base Registers The Ethernet I/O space consists of sixteen locations whose base address is determined in PCMCIA mode by the Ethernet I/O Base Registers, and in ISA mode by the default value of the Base Register (either reset or serial EEPROM default in ISA mode only). The Ethernet I/O space can be configured as an 8 or 16 bit space, and is similar to the SMC91C95, SMC91C92, etc. I/O space. To limit the I/O space requirements to 16 locations, the registers are split into six banks. The last word of the I/O area is shared by all banks and can be used to change the bank in use. Banks 0 through 3 functionally correspond to the SMC91C95 banks, while Banks 4 and 5 allow access to the multifunction registers in ISA mode.
90
FUNCTIONAL DESCRIPTION OF THE BLOCKS
MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and deallocation, it interfaces the arbiter only. The MMU deals with a single ported memory and is not aware of the fact that there are two entities requesting allocation and actually accessing memory. The mapping function done by the MMU is only a function of the packet number accessed and of the offset within that packet being accessed. It is not a function of who is requesting the access or the direction of the access. To accomplish that, memory accesses as well as MMU allocation and de-allocation requests are arbitrated by the arbiter block before reaching the MMU. Memory allocation could take some time, but the ALLOC INT bit in Interrupt Status Register is negated immediately upon allocation request, allowing the system to poll that register at any time. Memory de-allocation command completion indication is provided via the BUSY bit, readable through the MMU command register. The mapping and queuing functions of the MMU rely on the uniqueness of the packet number assigned to the requester. For that purpose the packet number assignment is centralized at the MMU, and a number will not be reused until the memory associated with it is released. It is clear that a packet number should not be released while the number is in the TX or RX packet queue. The TX and RCV FIFOs are deep enough to handle the total number of packets the MMU can allocate, therefore there is no need for the programmer or the hardware to check FIFO full conditions. ARBITER The function of the arbiter is to sequence packet RAM accesses as well as MMU requests in such a way that the on-chip single ported RAM and a single MMU can be shared by two parties. One party is the host CPU and the other party is the CSMA/CD block. The arbiter is address transparent, namely, any address can be accessed at any time. In order to exploit the sequential nature of the access, and minimize the access time on the system side, the CPU cycle is buffered by the Data Register rather than go directly to and from memory. Whenever a write cycle is performed, the data is written into the Data Register and will be written into memory as a result of that operation, allowing the CPU cycle to complete before the arbitration and memory cycle are complete. Whenever a read cycle is performed, the data is provided immediately from the Data Register, without having to arbitrate and complete a memory cycle. The present cycle results in an arbitration request for the next data location. Loading the pointer causes a similar pre-fetch request. This type of read-ahead and write-behind arbitration allows the controller to have a very fast access time, and would work without wait states for as long as the cycle time spec. is satisfied. The values are 40 ns access time, and 185ns cycle time. By the same token, CSMA/CD cycles might be postponed. The worst case CSMA/CD latency for arbiter service is one memory cycle.
91
The arbiter uses the pointer register as the CPU provided address, and the internal DMA address from the CSMA/CD side as the addresses to be provided to the MMU. The data path routed by the arbiter goes between memory (the data path does not go through the MMU) on one side and either the CPU side bus or the data path of the CSMA/CD core. The data path between memory and the Data Register is in fact buffered by a small FIFO in each direction. The FIFOs beneath the Data Register can be read and written as bytes or words, in any sequential combination. The presence of these FIFOs makes sure that word transfers are possible on the system bus even if the address loaded into the pointer is odd. BUS INTERFACE The bus interface handles the data, address and control interfaces as a superset of the ISA and PCMCIA specifications and allows 8 or 16 bit adapters to be designed with the SMC91C95 with no glue to interface to the ISA or PCMCIA bus. The functions done in this block are address decoding for I/O and ROM memory (including address relocation support) for ISA, data path routing, sequential memory address support, optional wait state generation, boot ROM support, EEPROM setup function, bus transceiver control, and interrupt generation/selection. For ISA, I/O address decoding is done by comparing A15-A4 to the I/O BASE address determined in part by the upper byte of the BASE ADDRESS REGISTER, and also requiring that AEN be low. If the above address comparison is satisfied and the SMC91C95 is in 16 bit mode, nIOCS16 will be asserted (low).
A valid comparison does not yet indicate a valid I/O cycle is in progress, as the addresses could be used for a memory cycle, or could even glitch through a valid value. Only when nIORD or nIOWR are activated the I/O cycle begins. In PCMCIA mode, A4-A15 are ignored for I/O decodes, which rely on the PCMCIA host decoding for the slot. Input A10 for ISA is used as an output (nFWE) for PCMCIA to enable Flash Memory Write for programming the attribute memory. It is valid only when nWE is 0 and COR2 is 1. nA11/nFCS is used to select the Flash Memory Chip. WAIT STATE POLICY The SMC91C95 can work on most system buses without having to add wait states. The two parameters that determine the memory access profile are the read access time and the cycle time into the Data Register. The read access time is 40ns and the cycle time is 185ns. If any one of them does not satisfy the application requirements, wait states should be added. If the access time is the problem, IOCHRDY should be negated for all accesses to the SMC91C95. This can be achieved by programming the NO WAIT ST bit in the configuration register to 0. The SMC91C95 will negate IOCHRDY for 100ns to 150ns on every access to any register. If the cycle time is the problem, programming NO WAIT ST as described before will solve it but at the expense of slowing down all accesses. The alternative is to let the SMC91C95 negate IOCHRDY only when the Data Register FIFOs require so. Namely, if NO WAIT ST is set, IOCHRDY will only be negated if a Data Register read cycle starts and there is less than a full word in the read FIFO, or if a
92
write cycle starts and there is more than two bytes in the write FIFO. The cycle time is defined as the time between leading edges of read from the Data Register, or equivalently between trailing edges of write to the Data Register. For example, in an ISA system the cycle time of a 16 bit transfer will be at least 2 clocks for the I/O access to the SMC91C95 + one clock for the memory cycle) = 3 clocks. In absolute time it means 375ns for a 8MHz bus, and 240ns for a 12.5 MHz bus. The cycle time will not increase when configured for full duplex mode, because the CSMA/CD memory arbitration requests are sequenced by the DMA logic and never overlap. DMA BLOCK The DMA block resides between the CSMA/CD block and the arbiter. It can interface both the data path and the control path of the CSMA/CD block for different operations. Its functions include the following: * * * * * * * * Start transmission process into the CSMA/CD block. Generate CSMA/CD side addresses for accessing memory during transmit and receive operations. Generate MMU memory requests and verify success. Compute byte count and write it in first locations of receive packet. Write transmit status word in first locations of transmit packet. Determine if enough memory is available for reception. De-allocate transmit memory after suitable completion. De-allocate receive memory upon error conditions.
* *
Initiate retransmissions upon collisions (if less than 16 retries). Terminate reception and release memory if packet is too long.
The specific nature of each operation and its trigger event are: 1) TX operations will begin if TXENA is set and TX FIFO is not empty. The DMA logic does not need to use the TX PACKET NUMBER, it goes directly from the FIFO to the MMU. However the DMA logic controls the removal of the PACKET NUMBER from the FIFO. Generation of CSMA/CD side addresses into memory: Independent 11 bit counters are kept for transmit and receive in order to allow full-duplex operation. MMU requests for allocation are generated by the DMA logic upon reception. The initial allocation request is issued when the CSMA block indicates an active reception. If allocation succeeds, the DMA block stores the packet number assigned to it, and generates write arbitration requests for as long as the CSMA/CD FIFO is not empty. In parallel the CSMA/CD completes the address filtering and notifies the DMA of an address match. If there is no address match, the DMA logic will release the allocated memory and stop reception. When the CSMA/CD block notifies the DMA logic that a receive packet was completed, if the CRC is OK, the DMA will either write the previously stored packet number into the RX PACKET NUMBER FIFO (to be processed by the CPU), or if the CRC is bad the DMA will just issue a release command to the MMU (and the CPU will never see that packet).
2)
3)
4)
93
Packets with bad CRC can be received if the RCV_BAD bit in the configuration register is set. 5) If AUTO_RELEASE is set, a release is issued by the DMA block to the MMU after a successful transmission (TX_SUCC set), and the TX completion FIFO is clocked together with the TX FIFO preventing the packet number from moving into the TX completion FIFO. Based on the RX counter value, if a receive packet exceeds 1532 bytes, reception is stopped by the DMA and the RX ABORT bit in the Receive Control Register is set. The memory allocated to the packet is automatically released. If an allocation fails, the CSMA/CD block will activate RX_OVRN upon detecting a FIFO full condition. RXEN will stay active to allow reception of subsequent packets if memory becomes available. The CSMA/CD block will flush the FIFO upon the new frame arrival.
the Fifo Ports Register. The CPU can remove a packet number from this FIFO by issuing a TX INT acknowledge. The CPU can determine if this FIFO is empty by reading the TX INT bit or the FIFO Ports Register. The receive packet FIFO stores the packet numbers already received into memory, in the order they were received. The FIFO is advanced (written) by the DMA block upon reception of a complete valid packet into memory. The number is determined the moment the DMA block first requests memory from the MMU for that packet. The first receive packet number in the FIFO can be read via the Fifo Ports Register, and the data associated with it can be accessed through the receive area. The packet number can be removed from the FIFO with or without an automatic release of its associated memory. The FIFO is read out upon CPU command (remove packet from top of RX FIFO, or remove and release command) after processing the receive packet in the receive area. The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of packets the SMC91C95 can handle (18). The guideline is software transparency; the software driver should not be aware of different devices or FIFO depths. If the MMU memory allocation succeeded, there will be room in the transmit FIFO for enqueuing the packet. Conversely if there is free memory for receive, there should be room in the receive FIFO for storing the packet number. Note that the CPU can enqueue a transmit command with a packet number that does not follow the sequence in which the MMU assigned packet numbers. For example, when a transmission failed and it is retried in software, or when a receive packet is modified and sent back to the network.
6)
7)
PACKET NUMBER FIFOS The transmit packet FIFO stores the packet numbers awaiting transmission, in the order they were enqueued. The FIFO is advanced (written) when the CPU issues the "enqueue packet number command", the packet number to be written is provided by the CPU via the Packet Number Register. The number was previously obtained by requesting memory allocation from the MMU. The FIFO is read by the DMA block when the CSMA/CD block is ready to proceed on to the next transmission. By reading the TX EMPTY INT bit the CPU can determine if this FIFO is empty. The transmit completion FIFO stores the packet numbers that were already transmitted but not yet acknowledged by the CPU. The CPU can read the next packet number in this FIFO from
94
PACKET NUMBER RX FIFO PACKET NUMBER REGISTER
WR
RD
TX FIFO
RX FIFO
TX COMPLETION
RX PACKET NUMBER
FIFO
TX DONE PACKET NUMBER CPU ADDRESS CSMA ADDRESS
FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS
LOGICAL ADDRESS
MMU COMMAND REGISTER DECODER ALLOCATE RELEASE
95
ALLOCATION RESULT REGISTER PACK # OUT
PACKET #
ALLOCATE RELEASE
CSMA/CD MMU
DMA
PACK # OUT PHYSICAL ADDRESS
RAM
CSMA BLOCK The CSMA/CD block is first interfaced via its control registers in order to define its operational configuration. From then on, the DMA interface between the CSMA/CD block and memory is used to transfer data to and from its data path interface. For transmit, the CSMA/CD block will be asked to transmit frames as soon as they are ready in memory. It will continue transmissions until any of the following transmit error occurs: a) b) c) d) e) 16 collisions on same frame (half duplex mode) Late collision (half duplex mode) Lost Carrier sense and MON_CSN set Transmit Under run SQET error and STP_SQET set
Note that the receive status word of any packet is available only through memory and is not readable through any other register. In order to let the CPU know about receive overruns, the RX_OVRN bit is latched into the Interrupt Status Register, which is readable by the CPU at any time. The address filtering is done inside the CSMA/CD block. A packet will be received if the destination address is broadcast, or if it is addressed to the individual address of the SMC91C95, or if it is a multicast address and ALMUL bit is set, or if it is a multicast address matching one of the multicast table entries. If the PRMS bit is set, all packets are received. The CSMA/CD block is a full duplex machine, and when working in full duplex mode, the CSMA/CD block will be simultaneously using its data path transmit and receive interfaces. Statistical counters are kept by the CSMA/CD block, and are readable through the appropriate register. The counters are four bits each, and can generate an interrupt when reaching their maximum values. Software can use that interrupt to update statistics in memory, or it can keep the counter interrupt disabled, while relying on the transmit interrupt routine reading the counters. Given that the counters can increment only once per transmit, this technique is a good complement for the single interrupt per sequence strategy. The interface between the CSMA/CD block and memory is word oriented. Two bi-directional FIFOs make the data path interface. Whenever a normal collision occurs (less than 16 retries - half duplex mode), the CSMA/CD will trigger the backoff logic and will indicate the DMA logic of the collision. The DMA is responsible for restarting the data transfer into the CSMA/CD block regardless of whether the collision happened on the preamble or not.
In that case TXENA will be cleared and the CPU should restart the transmission by setting it again. If a transmission is successful, TXENA stays set and the CSMA/CD is provided by the DMA block with the next packet to be transmitted. For receive, the CPU sets RXEN as a way of starting the CSMA/CD block receive process. The CSMA/CD block will send data after address filtering through the data path to the DMA block. Data is transferred into memory as it is received, and the final check on data acceptance is the CRC checking done by the CSMA/CD block. In any case, the DMA takes care of requesting/releasing memory for receive packets, as well as generating the byte count. The receive status word is provided by the CSMA/CD block and written in the first location of the receive structure by the DMA block. If configured for storing CRC in memory, the CSMA/CD unit will transfer the CRC bytes through the DMA interface, and then will be treated like regular data bytes.
96
Only when 16 retries are reached, the CSMA/CD block will clear the TXENA bit, and CPU intervention is required. The DMA will not automatically restart data transfer in this case, nor will it transmit the next enqueued packet until TXENA is set by the CPU. The DMA will move the packet number in question from the TX FIFO into the TX completion FIFO. NETWORK INTERFACE The SMC91C95 includes both an AUI interface for thick and thin coax applications and a 10BASE-T interface for twisted pair applications. Functions common to both are: 1. Manchester encoder/decoder to convert NRZ data to Manchester encoded data and back. A 32 ms jabber timer to prevent inadvertently long transmissions. When 'jabbing' occurs, the transmitter is disabled, automatic loopback is disabled (in 10BASE-T mode), and a collision indication is given to the controller. The interface 'unjabs' when the transmitter has been idle for a minimum of 256 ms. A phase-lock loop to recover data and clock from the Manchester data stream with up to plus or minus 18ns of jitter. Diagnostic loopback capability. LED drivers for collision, transmission, reception, and jabber.
transmission, data is automatically looped back to the receiver except during collision periods, in which case the input to the receiver is network data. During collisions, should the receive input go idle prior to the transmitter going idle, input to the receiver switches back to the transmitter within 9 bit times. Following transmission, the transmitter performs a SQE test. This test exercises the collision detection circuitry within the 10BASE-T interface. In full duplex mode, carrier sense is asserted during receive activity only. The receiver monitors the media at all times. It recovers the clock and data and passes it along to the controller. In the absence of any receive activity, the transmitter is looped back to the receiver. In addition, the receiver performs automatic polarity correction. The 10BASE-T interface performs link integrity tests per section 14.2.1.7 of 802.3, using the following values: 1. 2. 3. 4. Link_loss_timer: 64 ms Link_test_min_timer: 4 ms Link_count: 2 Link_test_max_timer: 64 ms
2.
3.
The state of the link is reflected in the EPHSR. AUI The SMC91C95 also provides a standard 6 wire AUI interface to a coax transceiver. PHYSICAL INTERFACE The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T transceiver. The ENDEC also provides a standard 6-pin AUI interface to an external coax transceiver for 10BASE-T and 10BASE-5 applications. The signals between MAC and the PHY can be routed to pins by asserting the nXENDEC pin low. This feature allows the interface to an external ENDEC and transceiver. The PHY functions
4. 5.
10BASE-T The 10BASE-T interface conforms to the twisted pair MAU addendum to the 802.3 specification. On the transmission side, it converts the NRZ data from the controller to Manchester data and provides the appropriate signal level for driving the media. Signal are predistorted before transmission to minimize ISI. In half duplex mode, the collision detection circuitry monitors the simultaneous occurrence of received signals and transmitted data on the media. During
97
can be divided into transmit and receive functions. Transmit Functions Manchester Encoding The PHY encodes the transmit data received from the MAC. The encoded data is directed internally to the selected output driver for transmission over the twisted-pair network or the AUI cable. Data transmission and encoding is initiated by the Transmit Enable input, TXE, going low. Transmit Drivers The encoded transmit data passes through to the transmit driver pair, TPETXP(N), and its complement, TPETXDP(N). Each output of the transmit driver pair has a source resistance of 10 ohms maximum and a current rating of 25 mA maximum. The degree of predistortion is determined by the termination resistors; the equivalent resistance should be 100 ohms. Jabber Function This integrated function prevents the DTE from locking into a continuous transmit state. In 10BASE-T mode, if transmission continues beyond the specified time limit, the jabber function inhibits further transmission and asserts the collision indicator nCOLL. The limits for jabber transmission are 20 to 15 ms in 10BASE-T mode. In the AUI mode, the jabber function is performed by the external transceiver. SQE Function In the 10BASE-T mode, the PHY supports the signal quality error (SQE) function. At the end of a transmission, the PHY asserts the nCOLL signal for 10+/-5 bit times beginning 0.6 to 1.6ms after the last positive transition of a transmitted frame. In the AUI mode, the SQE
function is transceiver.
performed
by
the
external
Receive Functions Receive Drivers Differential signals received off the twisted-pair network or AUI cable are directed to the internal clock recovery circuit prior to being decoded for the MAC. Manchester Decoder and Clock Recovery The PHY performs timing recovery and Manchester decoding of incoming differential signals in 10BASE-T or AUI modes, with its built-in phase-lock loop (PLL). The decoded (NRZ) data, RXD, and the recovered clock, RXCLK, becomes available to the MAC, typically within 9 bit times (5 for AUI) after the assertion of nCRS. The receive clock, RXCLK, is phase-locked to the transmit clock in the absence of a received signal (idle). Squelch Function The integrated smart squelch circuit employs a combination of amplitude and timing measurements to determine the validity of data received off the network. It prevents noise at the differential inputs from falsely triggering the decoder in the absence of valid data or link test pulses. Signal levels below 300mV (180mV for AUI) or pulse widths less than 15ns at the differential inputs are rejected. Signals above 585mV (300mV for AUI) and pulse widths greater than 30ns will be accepted. When using the extended cable mode with 10BASE-T media which extends beyond the standard limit of 100 meters, the squelch level can optionally be set to reject signals below 180mV and accept signals above 300mV. If the input signal exceeds the squelch requirements, the carrier sense output, nCRS, is asserted.
98
Reverse Polarity Function In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. Collision Detection Function In the 10BASE-T mode, while in half duplex, a collision state is indicated when there are simultaneous transmissions and receptions on the twisted pair link. During a collision state, the nCOLL signal is asserted. If the received data ends and the transmit control signal is still active, the transmit data is sent to the MAC within 9 bit times. The nnCOLL signal is deasserted within 9 bit times after the collision terminates. In the AUI mode, the external
transceiver sends a 10MHz signal to the PHY upon detection of a collision. Link Integrity The PHY test for a faulty twisted-pair link. In the absence of transmit data, link test pulses are tranmsitted every 16+/-18ms after the end of the last transmission or link pulse on the twisted pair medium. If neither valid data nor link test pulses are received within 10 to 150ms, the link is declared bad and both data transmission as well as the operational loopback function are disabled. The Link Integrity function can be disabled for pre10BASE-T twisted-pair networks.
99
BOARD SETUP INFORMATION ISA MODE The following parameters are obtained from the EEPROM as board setup information: ETHERNET INDIVIDUAL ADDRESS I/O BASE ADDRESS ROM BASE ADDRESS 8/16 BIT ADAPTER 10BASE-T or AUI INTERFACE INTERRUPT LINE SELECTION All the above mentioned values are read from the EEPROM upon hardware reset. Except for the INDIVIDUAL ADDRESS, the value of the IOS switches determines the offset within the EEPROM for these parameters, in such a way that many identical boards can be plugged into the same system by just changing the IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the SMC91C95. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, ROM BASE, INTERRUPT) that can always be used regardless of the EEPROM based value being programmed. This value will be used if all IOS pins are left open or pulled high. The EEPROM is arranged as a 64 x 16 array. The specific target device is the 9346 1024-bit Serial EEPROM. All EEPROM accesses are done in words. All EEPROM addresses shown are specified as word addresses. REGISTER Configuration Register Base Register EEPROM WORD ADDRESS IOS Value * 4
(IOS Value *4) + 1
INDIVIDUAL ADDRESS 20-22 hex If IOS2-IOS0=7, only the INDIVIDUAL ADDRESS is read from the EEPROM. Currently assigned values are assumed for the other registers. These values are default if the EEPROM read operation follows hardware reset. The EEPROM SELECT bit is used to determine the type of EEPROM operation: a) normal or b) general purpose register. a) NORMAL EEPROM OPERATION EEPROM SELECT bit = 0 -
On EEPROM read operations (after reset or after setting RELOAD high) the CONFIGURATION REGISTER and BASE REGISTER are updated with the EEPROM values at locations defined by the IOS2-0 pins. The INDIVIDUAL ADDRESS registers are updated with the values stored in the INDIVIDUAL ADDRESS area of the EEPROM. On EEPROM write operations (after setting the STORE bit) the values of the CONFIGURATION REGISTER and BASE
100
REGISTER are written in the EEPROM locations defined by the IOS2-0 pins. The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and STORE) are used to control the EEPROM. Their values are not stored nor loaded from the EEPROM. b) GENERAL PURPOSE REGISTER EEPROM SELECT bit = 1 -
DIAGNOSTIC LEDs The following LED drive signals are available for diagnostic and installation aid purposes: nTXLED - Activated by transmit activity. nBSELED - Board select LED. Activated when the board space is accessed, namely on accesses to the SMC91C95 register space or the ROM area decoded by the SMC91C95. The signal is stretched to 125 msec. nRXLED - Activated by receive activity. nLINKLED - Reflects the link integrity status. ARBITRATION CONSIDERATIONS
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER. On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits. RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the SMC91C95 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. NOTE: If no EEPROM is connected to the SMC91C95, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value.
The arbiter exploits the sequential nature of the CPU accesses to provide a very fast access time. Memory bandwidth considerations will have an effect on the CPU cycle time but no effect on access time. For normal 8 MHz, 10 MHz and 12.5 MHz ISA buses as well as EISA normal cycles the SMC91C95 can be accessed without negating ready. When write operations occur, the data is written into a FIFO. The CPU cycle can complete immediately, and the buffered data will be written into memory later. The memory arbitration request is generated as a function of that FIFO being not empty. The nature of the cycle requested (byte/word) is determined by the lsb of the pointer and the number of bytes in the FIFO. When read operations occur, words are prefetched upon pointer loading in order to have at least a word ready in the FIFO to be read. New pre-fetch cycles are requested as a function of the number of bytes in the FIFO.
101
For example, if an odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately a full word is pre-fetched completing three bytes into the FIFO. If the CPU reads a word, one byte will be left again a new word is pre-fetched. In the case of write, if an odd pointer value is loaded, and a full word is written, the FIFO holds two bytes, the first of which is immediately written into an odd memory location. If by that time another byte or
word was written, there will be two or three bytes in the FIFO and a full word can be written into the now even memory address. When a CSMA/CD cycle begins, the arbiter will route the CSMA/CD DMA addresses to the MMU as well as the packet number associated with the operation in progress. In full-duplex mode, receive and transmit requests are alternated in such a way that the CPU arbitration cycle time is not affected.
102
16 BITS IOS2-0 000 WORD ADDRESS 0h 1h CONFIGURATION REG. BASE REG.
001
4h 5h
CONFIGURATION REG. BASE REG.
010
8h 9h
CONFIGURATION REG. BASE REG.
011
Ch Dh
CONFIGURATION REG. BASE REG.
100
10h 11h
CONFIGURATION REG. BASE REG.
101
14h 15h
CONFIGURATION REG. BASE REG.
110
18h 19h
CONFIGURATION REG. BASE REG.
XXX
20h 21h 22h
IA0-1 IA2-3 IA4-5
FIGURE 17 - 64 X 16 SERIAL EEPROM MAP FOR ISA MODE
103
OPERATIONAL DESCRIPTION
MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ...................................................................................... 0 o C to +70o C Storage Temperature Range ....................................................................................-55o C to +150o C Lead Temperature Range (soldering, 10 seconds) .................................................................. +325o C Positive Voltage on any pin, with respect to Ground ...........................................................Vcc + 0.3V Negative Voltage on any pin, with respect to Ground .................................................................. -0.3V Maximum Vcc ............................................................................................................................... +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0o C - 70o C, Vcc = +5.0 V 10%) PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level VILI VIHI 2.0 0.8 V V TTL Levels SYMBO L MIN TYP MAX UNITS COMMENTS
VILIS VIHIS VHYS 2.2 250
0.8
V V mV
Schmitt Trigger Schmitt Trigger
VILCK VIHCK 3.0
0.4
V V
104
PARAMETER Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage IP Type Buffers Input Current ID Type Buffers Input Current I/04 Type Buffer Low Output Level High Output Level Output Leakage I/024 Type Buffer Low Output Level High Output Level Output Leakage 024 Type Buffer Low Output Level High Output Level Output Leakage 04 Type Buffer Low Output Level High Output Level Output Leakage
SYMBO L
MIN
TYP
MAX
UNITS
COMMENTS
IIL IIH
-10 -10
+10 +10
A A A A
VIN = 0 VIN = VCC
IIL
-150
-75
VIN = 0
IIH
+75
+150
VIN = VCC
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 4 mA IOH = -2 mA VIN = 0 to VCC
+10
A
VOL VOH IOL 2.4 -10
0.5
V V
IOL = 24 mA IOH = -12 mA VIN = 0 to VCC
+10
A
VOL VOH IOL 2.4 -10
0.5
V V
IOL = 24 mA IOH = -12 mA VIN = 0 to VCC
+10
A
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 4 mA IOH = -2 mA VIN = 0 to VCC
+10
A
105
PARAMETER OD16 Type Buffer Low Output Level Output Leakage OD162 Type Buffer Low Output Level High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby
SYMBO L
MIN
TYP
MAX
UNITS
COMMENTS
VOL IOL -10
0.5 +10
V A
IOL = 16 mA VIN = 0 to VCC
VOL VOH IOL 2.4 -10
0.5
V V
IOL = 16 mA IOH = -2 mA VIN = 0 to VCC
+10
A
VOL IOL ICC ICSBY -10 60 8
0.5 +10 95
V A mA mA
IOL = 24 mA VIN = 0 to VCC All outputs open
CAPACITANCE TA = 25oC; fc = 1MHz; VCC = 5V LIMITS TYP MAX 20
PARAMETER Clock Input Capacitance
SYMBO L CIN
MIN
UNIT pF
TEST CONDITION All pins except pin under test tied to AC ground
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
106
PARAMETER Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage
MIN 10BASE-T 300 0 2
TYP 100 400 2.5
MAX
UNITS mV mV V ohms mV mV V mV mV V mV V mV mV
0.585 AUI 60 240 0.85
585 VDD 3 10 50 100 3
Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output Voltage (R=78) Transmitter Backswing Voltage to Idle Input Differential Voltage Output Short Circuit (to VCC or GND) Current Differential Idle Voltage (measured 8.0 s after last positive transition of data frame)
180 0 0.45 0.3
300 VDD 1.2 100 1.2 150 40
CAPACITIVE LOAD ON OUTPUTS nIOCS16, IOCHRDY INTRO-INTR3 All other outputs 240 pF 120 pF 45 pF
107
TIMING DIAGRAMS
t1 t2 A[5:0], nREG 0 min nCE1 t3
nOE
30 max
t4 t5 t6 5 max
D[15:0]
DATA VALID
t1 t2 t3 t4 t5 t6
Parameter Address Access Time nREG Access Time nCE1 Access Time nOE Access Time Output Disable Time from nCE1 high Output disable Time from nOE high
Min
Typ
Max 300 300 300 150 100 100
Units ns ns ns ns ns ns
NOTE: Applies only when nWAIT is asserted by the SMC91C95. FIGURE 18 - PCMCIA MEMORY READ TIMING
108
250 min
A[5:0], nREG 0 min nCE1 t3 nOE t1 t2 nWE t5 D[15:0 (Din)] t6 t7 t4 20 min
Parameter t1 t2 t3 t4 t5 t6 t7 nWE Pulse Width Address/nREG Setup Time to nWE Low Address/nREG Setup Time to nWE High nCE1 Low to nWE High Setup Time Data to nWE High Setup Time Data Hold Time from nWE High Write Recovery Time (Address, nREG Hold from nWE High)
Min 150 30 180 180 80 30 30
Typ
Max
Units ns ns ns ns ns ns ns
NOTE: Minimum write pulse width must be met whether or not nWAIT is asserted by the SMC91C95 FIGURE 19 - PCMCIA MEMORY WRITE TIMING
109
A[15:0] t18 nMCS t15 t3 nREG t2 nCE t16 nIORD t1 nINPACK t8 t36 nIOIS16 t12 t13 t11 t9 t4 t6 t10 t17 t7 t19 t5 t20
t14 D[15::0]
FIGURE 20 - I/O READ TIMING (Table on the following page)
110
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t36 t15 t16 t17 t18 t19 t20
Parameter Address setup before nIORD low nCEI, nCE2 setup before nIORD low nREG setup before nIORD low nIORD low width Address hold from nIORD high nCE1, nCE2 hold following nIORD high nREG hold following nIORD high Address valid to nINPACK low nCE1, nCE2 low to nINPACK low nREG low to nINPACK low nIORD low to nINPACK low Address valid to nIOIs16 valid nIORD low to data valid Data hold following nIORD nIOIS16 delay from address Address valid to nMCS low nCE1 low to nMCS low nREG low to nMCS low Address invalid to nMCS high nCE1 high to nMCS high nREG high to nMCS high
Min 70 5 5 165 20 20 0
Typ
Max
115 50 50 45 35 100 0 35 20 40 40 100 40 40
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
111
A[15:0]
nMCS
t30 t23 t25 t27
t33 t35
nREG
t32 t22
t34 nCE1 nCE2 nIOWR t21 nIOIS16 t28 t29 D[15::0] t36 t31 t24 t26
FIGURE 21 - (I/O WRITE TIMING) (Table on the following page)
112
t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36
Parameter Address setup before nIOWR low nCE1, nCE2 setup before nIOWR low nREG setup before nIOWR low nIOWR low width Address hold from nIOWR high nCE1, nCE2, hold following nIOWR high nREG hold following nIOWR high Address valid to nIOIS16 valid Data hold following nIOWR Address valid to nMCS low nCE1 low to nMCS low nREG low to nMCS low Address invalid to nMCS high nCE1 high to nMCS high nREG high to nMCS high nIOIS16 delay from address
Min 70 5 5 165 20 20 0 30
Typ
Max
35 100 40 40 100 40 40 35
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
113
t60 A0-9,A15 t62 nREG t64 valid
t63
t60 valid
t61
nCE1
t57 nWE nOE t59 t65 valid
t58 D0-7 valid
Parameter t57 t58 t59 t60 t61 t62 t63 t64 t65 Write Data Setup to nWE Rising Write Data Hold after nWE Rising nOE Low to Valid Data Address, nREG Setup to nWE Active Address, nREG Hold after nOE Inactive Address, nREG Setup to nOE Active Address, nREG Hold after Control Inactive nCE1 Setup to nWE Rising nCE1 Low to Valid Data
min 30 9
typ
max
units ns ns ns ns ns ns ns ns ns
40 25 15 25 15 60 0
50
FIGURE 22 - CARD CONFIGURATION REGISTERS - READ/WRITE PCMCIA MODE (A15=1)
114
t51 A0-9,A15 t48 nREG t49 nCE1,nCE valid
t52
t20
t50
t53 nIORD t47 D0-15 t46 nINPAC valid t46
Parameter t46 t47 t48 t20 t49 t50 t51 t52 t53 nIORD Delay to nREG Low to Control nCE1,nCE2 Setup to Control Cycle Time (No Wait nREG Hold after Control nCE1,nCE2 Hold after Control Address Setup to Control Address Hold after Control nIORD Active to Data
min 0 5 5 185 0 15 25 15 0
typ
max 35
units ns ns ns ns ns ns ns ns ns
40
FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLES
115
t51 A0-9,A15 t47 valid
t52
nREG
t49
t48 nCE1,nCE2
t50
t20 t54 nIOWR valid t55
D0-15
Parameter t47 t48 t49 t50 t51 t52 t20 t54 t55 nREG Low Setup to Control Active nCE1,nCE2 Setup to Control Active nREG Hold after Control Inactive nCE1,nCE2 Hold after Control Inactive Address Setup to Control Active Address Hold after Control Inactive Cycle Time (No Wait States) Write Data Setup to nIOWR Rising Write Data Hold after nIOWR Rising
min 5 5 0 15 25 15 185 30 9
typ
max
units ns ns ns ns ns ns ns ns ns
FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES
116
A0-9,A15 nREG nCE1
valid
valid
t67 t67 t67 nFCS nWE
t67 t67 t67
t67 t67 t67 t67
t67 t67
t66 nFWE nOE
t66
Parameter t66 t67 nWE to nFWE Delay Address, nREG, nCE1 Delay to nFCS
min 0 0
typ
max 20 25
units ns ns
FIGURE 25 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0)
117
nMPWDN]
MRINGOUTB t1 t2
t1 t2
Parameter MRINGOUTB Pulse Entering Powerdown MRINGOUTB Pulse Exiting Powerdown
Min
Typ
Max 7.5 7.5
Units ms ms
FIGURE 26 - RINGOUT FOR L39/C39 ROCKWELL MODEMS ENTERING/EXITING POWERDOWN
118
A0-15 AEN, nSBHE t15 nIOCS16
VALID ADDRESS t4
VALID ADDRESS
t3 nIORD
t20
t5 D0-15
t6 VALID DATA OUT Z VALID DATA OUT Z
Parameter t3 t4 t5 t6 t15 t20 Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive nIORD Low to Valid Data nIORD High to Data Floating A4-A15, AEN Low, BALE High to nIOCS16 Low Cycle time*
min 25 20
typ
max
units ns ns
40 30 25 185
ns ns ns ns
BALE Tied High IOCHRDY not used - t20 has to be met *Note: The cycle time is defined only for consecutive accesses to the Data Register. These values assume that IOCHRDY is not used.
FIGURE 27 - ISA CONSECUTIVE READ CYCLES
119
A0-15 AEN, nSBHE t15 nIOCS16 t3 nIOWR
VALID ADDRESS t4
VALID ADDRESS
t20
t8 t7 D0-15 VALID DATA IN VALID DATA
Parameter t3 t4 t7 t8 t15 t20 Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive Data Setup to nIOWR Rising Data Hold after nIOWR Rising A4-A15, AEN Low, BALE High to nIOCS16 Low Cycle time*
min 25 20 30 9
typ
max
units ns ns ns ns ns ns
25 185
BALE Tied High IOCHRDY not used - t20 has to be met *Note: The cycle time is defined only for consecutive accesses to the Data Register. These values assume that IOCHRDY is not used.
FIGURE 28 - ISA CONSECUTIVE WRITE CYCLES
120
A0-15 AEN, nSBHE
VALID ADDRESS
VALID ADDRESS
nIOCS16
t20 nIORD nIOWR t9 Z IOCHRDY Z t10
D0-D15
Z
VALID DATA
Z
VALID DATA
Z
Parameter t9 t10 t20 Control Active to IOCHRDY Low IOCHRDY Low Pulse Width* Cycle time**
min
typ
max 15
units ns ns ns
100 185
150
*Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed. **Note: The cycle time is defined only for accesses to the Data Register as follows: For Data Register Read - From nIORD falling to next nIORD falling For Data Register Write - From nIOWR rising to next nIOWR rising
FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES
121
A0-15 (ISA) AEN, nSBHE nIOCS16
VALID ADDRESS
nIORD
Z IOCHRDY
t9 t18 Z
t19 D0-D15 VALID DATA OUT
Parameter t9 t18 t19 Control Active to IOCHRDY Low IOCHRDY Width when Data is Unavailable at Data Register Valid Data to IOCHRDY Inactive
min
typ
max 15 575 225
units ns ns ns
IOCHRDY is used instead of meeting t20 and t43. "No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access.
FIGURE 30 - DATA REGISTER SPECIAL READ ACCESS
122
A0-15 (ISA) AEN, nSBHE nIOCS16 VALID ADDRESS
nIOWR
t9 IOCHRDY Z t18 Z
D0-D15
VALID DATA IN
Parameter t9 t18 Control Active to IOCHRDY Low IOCHRDY Width when Data Register is Full
min
typ
max 15 425
units ns ns
IOCHRDY is used instead of meeting t20 and t44. 'No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access.
FIGURE 31 - DATA REGISTER SPECIAL WRITE ACCESS
123
A0-15 (ISA) AEN nIOWR t3 nIORD
VALID ADDRESS t3
VALID ADDRESS
t7 t8 t5 D0-7 Z VALID DATA OUT Z VALID DATA IN typ max units ns ns ns ns
Parameter t3 t5 t7 t8 Address, nSBHE, AEN Setup to Control Active nIORD Low to Valid Data Data Setup to nIOWR Rising Data Hold after nIOWR Rising
min 25
40 30 9
FIGURE 32 - 8-BIT MODE REGISTER CYCLES
A0-19 t3 nMEMRD
ADDRESS VALID t4
D0-15
Z
Parameter t3 t4 t16 t17 Address Setup to Control Active Address Hold after Control Inactive nMEMRD Low to nROM Low nMEMRD High to nROM High
min 25 20 0 0
typ
max
units ns ns ns ns
25 30
BALE tied high
FIGURE 33 - EXTERNAL ROM READ ACCESS
124
t4 AEN
A0-15, nSBHE t1
VALID
t2
BALE nIOCS16
t15
nIORD nIOWR
t3
Parameter t1 t2 t3 t4 t15 Address, nSBHE Setup to BALE Falling Address, nSBHE Hold after BALE Falling Address, nSBHE, AEN Setup to Control Active AEN Hold after Control Inactive A4-A15, AEN Low, BALE High to nIOCS16 Low
min 20 20 25 20
typ
max
units ns ns ns ns
25
ns
t4 not needed. nIOCS16 not relevant in 8-bit mode.
FIGURE 34 - ISA REGISTER ACCESS WHEN USING BALE
125
A0-19 VALID
t1 t2 BALE
t3 nMEMRD
t16 nROM
t17
Parameter t1 t2 t3 t16 t17 Address Setup to BALE Falling Address Hold after BALE Falling Address Setup to Control Active nMEMRD Low to nROM Low nMEMRD High to nROM High
min 20 20 25
typ
max
units ns ns ns
25 30
ns ns
FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALE
126
EESK
EEDO
EEDI
EECS t21 t21
Parameter t21 EESK Falling to EEDO, EECS Changing
min 0
typ
max 100
units ns
9346 is typically the serial EEPROM used.
FIGURE 36 - EEPROM READ
127
EESK
EEDO
EEDI
EECS t21 t21
Parameter t21 EESK Falling to EEDO, EECS Changing
min
typ
max 100
units ns
9346 is typically the serial EEPROM used.
FIGURE 37 - EEPROM WRITE
128
ADDRESS
POINTER REGISTER
DATA REGISTER
nIOWR t44 nIORD
IOCHRDY/ nWAIT (Z) Parameter t44 Pointer Register Reloaded to a Word of Data Prefetched into Data Register min 2 * t20 typ max units ns
Note: If t44 is not met, IOCHRDY will be negated for the required time. This parameter can be ignored if IOCHRDY is connected to the system.
FIGURE 38 - MEMORY READ TIMING
ADDRESS
DATA REGISTER
POINTER REGISTER
nIOWR t45
Parameter t45 Last Access to Data Register to Pointer Reloaded
min 2 * t20
typ
max
units ns
FIGURE 39 - MEMORY WRITE TIMING
129
nTXEN
TXD
TXCLK t22 t22 Parameter t22 TXD, nTXEN Delay from TXCLK Falling min 0 typ max 40 units ns
FIGURE 40 - EXTERNAL ENDEC INTERFACE - START OF TRANSMIT
t23 RXD t24
RXCLK
nCRS t23
Parameter t23 t24 nCRS, RXD Setup to RXCLK Falling nCRS, RXD Hold after RXCLK Falling
min 10 30
typ
max
units ns ns
FIGURE 41 - EXTERNAL ENDEC INTERFACE - RECEIVE DATA (RXD SAMPLED BY FALLING RXCLK)
130
TPETXP t31 TPETXN t32 TPETXDN t33 TPETXDP TWISTED PAIR DRIVERS t33 t32 t31
TXP t34 TXN AUI DRIVERS t34
Parameter t31 t32 t33 t34 TPETXP to TPETXN Skew TPETXP(N) to TPETXDP(N) Delay TPETXDN to TPETXDP Skew TXP to TXN Skew
min -1 47 -1 -1.5
typ
max +1 53 +1 1.5
units ns ns ns ns
FIGURE 42 - DIFFERENTIAL OUTPUT SIGNAL TIMING (10BASE-T AND AUI)
131
1
0
1
0
1
0
1
0
1
0
RECP RECN t35 first bit decoded nCRS (internal) t36
1
0
1
0
1
0
1
0
1
0
TPERXP(N)
t37 nCRS (internal)
first bit decoded
t38
Parameter t35 t36 t37 t38
min
typ 25 70 25 500
max 30 100 30 550
units ns ns ns ns
15 Noise Pulse Width Reject (AUI) Carrier Sense Turn On Delay (AUI) 50 Noise Sense Pulse Width Reject (10BASE-T) 15 450 Carrier Sense Turn On Delay (10BASE-T)
FIGURE 43 - RECEIVE TIMING - START OF FRAME (AUI AND 10BASE-T)
132
last bit b a 1/0
TPERXP TPERXN
RECP RECN
t39 nCRS (internal)
Parameter t39 Receiver Turn Off Delay
min 200
typ
max 300
units ns
FIGURE 44 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T)
133
t40 t41
TPETXP TPETXN
last bit b a 1/0
TXP TXN
Parameter t40 t41 Transmit Output High to Idle in Half-Step Mode Transmit Output High before Idle in Half-Step Mode
min
typ
max 800
units ns ns
200
FIGURE 45 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T)
134
COLLP COLLN
t42 COL (internal)
t43
Parameter t42 t43 Collision Turn On Delay Collision Turn Off Delay
min
typ
max 50 350
units ns ns
FIGURE 46 - COLLISION TIMING (AUI)
135
He E
A2 A1 Y
Hd
D
L1 c e
0.08(0.003) M
b
0
GAGE PLANE
0.25
L
MILLIMETER SYMBOL MIN. NOM. 0.10 1.00 0.18 MAX. 0.15 1.05 0.23 0.20 14.00 14.00 0.40 15.90 15.90 0.45 16.00 16.00 0.60 1.00 0.08 0 7 0 16.10 16.10 0.75 0.626 0.626 0.018 14.10 14.10 MIN. 0.002 0.037 0.005 0.004 0.547 0.547 0.551 0.551 0.016 0.630 0.630 0.024 0.039 0.003 7 0.634 0.634 0.030 NOM. 0.004 0.039 0.007 MAX. 0.006 0.041 0.009 0.008 0.555 0.555 INCH
A1 A2 b c D E e Hd He
0.05 0.95 0.13 0.09 13.90 13.90
L
L1
Y 0
FIGURE 47 - VTQFP PACKAGE OUTLINE 136
300 Kennedy Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 231-6004
Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best product possible. SMC91C95 Rev. 08/08/96

▲Up To Search▲

Price & Availability of SMC91C95

	To Download SMC91C95 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .